ISP1761BE STEricsson, ISP1761BE Datasheet - Page 56

• Manufacturer Part Number: ISP1761BE
• Manufacturer: STEricsson

Specifications of ISP1761BE

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: LQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 55.
ISP1761_5
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit allocation
8.4.2 HcInterruptEnable register
R/W
R/W
R/W
31
23
15
0
0
0
Table 54.
This register allows enabling or disabling of the IRQ generation because of various events
as described in
Bit
5
4
3
2
1
0
R/W
R/W
R/W
30
22
14
0
0
0
Symbol
HCSUSP
-
DMAEOTINT
-
SOFITLINT
-
HcInterrupt - Host Controller Interrupt register (address 0310h) bit
description
Table
reserved
R/W
R/W
R/W
29
21
13
0
0
0
55.
…continued
Rev. 05 — 13 March 2008
[1]
Description
Host Controller Suspend: Indicates that the host controller has
entered suspend mode. The IRQ line will be asserted if the respective
enable bit in the HcInterruptEnable register is set.
0 — The host controller did not enter suspend mode.
1 — The host controller entered suspend mode.
If the Interrupt Service Routine (ISR) accesses the ISP1761, it will wake
up for the time specified in bits 31 to 16 of the Power Down Control
register.
reserved; write reset value
DMA EOT Interrupt: Indicates the DMA transfer completion. The IRQ
line will be asserted if the respective enable bit in the HcInterruptEnable
register is set.
0 — No DMA transfer is completed
1 — DMA transfer is completed
reserved; write reset value; value is zero just after reset and changes to
one after a short while
SOT ITL Interrupt: The IRQ line will be asserted if the respective
enable bit in the HcInterruptEnable register is set.
0 — No SOF event has occurred
1 — An SOF event has occurred
reserved; write reset value; value is zero just after reset and changes to
one after a short while
R/W
R/W
R/W
28
20
12
0
0
0
reserved
reserved
[1]
[1]
R/W
R/W
R/W
27
19
11
0
0
0
OTG_IRQ_
R/W
R/W
R/W
26
18
10
E
0
0
0
Hi-Speed USB OTG controller
ISO_IRQ_E
R/W
R/W
R/W
25
17
0
0
9
0
© NXP B.V. 2008. All rights reserved.
ISP1761
ATL_IRQ
R/W
R/W
R/W
_E
55 of 163
24
16
0
0
8
0