5962-8863604LA Cypress Semiconductor Corp, 5962-8863604LA Datasheet - Page 9

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5962-8863604LA

Manufacturer Part Number
5962-8863604LA
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of 5962-8863604LA

Lead Free Status / Rohs Status
Not Compliant
DSCC FORM 2234
APR 97
Mode
DEFENSE SUPPLY CENTER COLUMBUS
1/
2/
3/
4/
5/
NOTES:
1.
2.
3.
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43218-3990
X = don't care, but not to exceed V
During read operation, the output latches are loaded on a "0" to "1" transition of CP.
Pin 19 must be LOW prior to the "0" to "1" transition on CP (18) that loads the register.
Pin 19 must be HIGH prior to the "0" to "1" transition on CP (18) that loads the register.
Low to high clock transition required to enable outputs.
C
C
Tests are performed with rise and fall times of 5 ns or less.
All device test loads should be located within two inches of device outputs.
L
L
Read or Output disable
Output disable
Output disable
Read 1/ 2/ 3
INIT
includes probe and jig capacitance. C
= 5 pF for t
STANDARD
1/ 5/
HZC
and t
1/ 4/
1/
HZE
FIGURE 3. Output load circuit and test conditions.
.
A
2
X
X
X
X
PP
FIGURE 2. Truth table.
= 13.0 V, maximum.
L
CP
= 50 pF for all switching characteristics except t
X
X
X
X
Es
SIZE
V
V
X
X
A
IH
IL
INIT
V
V
V
V
IH
IH
IH
REVISION LEVEL
IL
E
V
V
V
X
IL
IH
IL
C
A
1
X
X
X
X
HZC
and t
SHEET
Outputs
Data out
High Z
High Z
1025th
word
5962-88636
HZE
.
9

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