CY23S09ZC-1 Cypress Semiconductor Corp, CY23S09ZC-1 Datasheet

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CY23S09ZC-1

Manufacturer Part Number
CY23S09ZC-1
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY23S09ZC-1

Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY23S09ZC-1
Manufacturer:
CY
Quantity:
131
Part Number:
CY23S09ZC-1H
Manufacturer:
ATMEL
Quantity:
20 402
Cypress Semiconductor Corporation
Document #: 38-07296 Rev. *C
Features
Functional Description
The CY23S09 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an eight-pin version of the
CY23S09. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
Block Diagram
• 10-MHz to 100-/133-MHz operating range, compatible
• Zero input-output propagation delay
• Multiple low-skew outputs
• Less than 200 ps cycle-to-cycle jitter is compatible with
• Test Mode to bypass PLL (CY23S09 only, see Select
• Available in space-saving 16-pin, 150-mil SOIC, 4.4 mm
• 3.3V operation, advanced 0.65µ CMOS technology
• Spread Aware™
with CPU and PCI bus frequencies
— Output-output skew less than 250 ps
— Device-device skew less than 700 ps
— One input drives five outputs (CY23S05)
— One input drives nine outputs, grouped as 4 + 4 + 1
Pentium
Input Decoding table on page 2)
TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
REF
(CY23S09)
S2
S1
REF
-based systems
PLL
PLL
CY23S09
CY23S05
Select Input
Low-Cost 3.3V Spread Aware™ Zero Delay Buffer
Decoding
MUX
3901 North First Street
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLK3
CLKO UT
CLK1
CLK2
CLK4
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The CY23S09 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the Select Input
Decoding table on page 2. If all output clocks are not required,
Bank B can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The CY23S09 and CY23S05 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 µA of current draw (for commercial temper-
ature devices) and 25.0 µA (for industrial temperature
devices). The CY23S09 PLL shuts down in one additional
case, as shown in the table below.
Multiple CY23S09 and CY23S05 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle-to-cycle jitter. The
input to output propagation delay on both devices is
guaranteed to be less than 350 ps, and the output to output
skew is guaranteed to be less than 250 ps.
The CY23S05/CY23S09 is available in two different configu-
rations, as shown in the ordering information on page 6. The
CY23S05-1/CY23S09-1 is the base part. The CY23S05-1H/
CY23S09-1H is the high-drive version of the -1, and its rise
and fall times are much faster than -1.
San Jose
CLKA1
CLKA2
CLKB1
CLKB2
GND
REF
V
S2
Pin Configuration
CLK2
CLK1
DD
GND
REF
SOIC/TSSOP/SSOP
,
1
2
3
4
5
6
7
8
Top View
CY23S09
1
2
3
4
CA 95134
CY23S05
Top View
SOIC
Revised September 21, 2004
15
14
13
12
11
10
16
9
8
7
6
5
CLK4
V
CLK3
CLKOUT
CLKOUT
CLKA4
CLKA3
V
GND
CLKB4
CLKB3
S1
DD
DD
408-943-2600
CY23S09
CY23S05
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CY23S09ZC-1 Summary of contents

Page 1

... S1 CY23S09 REF PLL CY23S05 Cypress Semiconductor Corporation Document #: 38-07296 Rev 100-/133-MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. ...

Page 2

Select Input Decoding for CY23S09 S2 S1 CLOCK A1– Three-state 0 1 Driven 1 0 Driven 1 1 Driven Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and ...

Page 3

Pin Description for CY23S05 Pin Signal [2] 1 REF [3] 2 CLK2 [3] 3 CLK1 4 GND [3] 5 CLK3 [3] 7 CLK4 [3] 8 CLKOUT Document #: 38-07296 Rev. *C Description Input reference frequency, 5V-tolerant input ...

Page 4

Maximum Ratings Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage (Except REF) ............–0. Input Voltage REF ............................................. −0. Operating Conditions for CY23S05SC-XX and CY23S09SC-XX Parameter V Supply Voltage DD T Operating ...

Page 5

Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H Parameter Description t1 Output Frequency [7] ÷ t Duty Cycle = [7] ÷ t Duty Cycle = [7] t3 Rise Time [7] t Fall Time 4 [7] t ...

Page 6

... Test Circuits Test Circuit # CLK out 0.1 µF OUTPUTS V DD 0.1 µF GND GND Ordering Information Ordering Code CY23S05SC-1 CY23S05SC-1H CY23S09SC-1 CY23S09SC-1H CY23S09ZC-1 CY23S09ZC-1H CY23S09OC-1 CY23S09OC-1H Lead Free CY23S05SXC-1 CY23S05SXC-1H CY23S09SXC-1 CY23S09SXC-1H CY23S09ZXC-1 CY23S09ZXC-1H CY23S09OXC-1 CY23S09OXC-1H Document #: 38-07296 Rev 2309–8 ...

Page 7

Package Diagrams 8 Lead (150 Mil) SOIC - S08 0.189[4.800] 0.196[4.978] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 16 Lead (150 Mil) SOIC 8 9 0.386[9.804] 0.393[9.982] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] Document #: 38-07296 Rev. *C 8-lead (150-Mil) SOIC ...

Page 8

... Document #: 38-07296 Rev. *C © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 9

Document History Page Document Title: CY23S09/CY23S05 Low-Cost 3.3V Spread Aware™ Zero Delay Buffer Document Number: 38-07296 REV. ECN NO. Issue Date ** 111147 11/14/01 *A 111773 02/20/02 *B 122885 12/22/02 *C 267849 See ECN Document #: 38-07296 Rev. *C Orig. ...

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