ISP1362BD NXP Semiconductors, ISP1362BD Datasheet
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IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...
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ISP1362 Single-chip Universal Serial Bus On-The-Go Controller Rev. 05 — 8 May 2007 1. General description The ISP1362 is a single-chip Universal Serial Bus (USB) On-The-Go (OTG) controller integrated with the advanced NXP Slave Host Controller and the NXP ISP1181B ...
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... NXP Semiconductors N Supports integrated physical 4096 bytes of multiconfiguration memory N Supports all four types of USB transfers: control, bulk, interrupt and isochronous N Supports multiframe buffering for isochronous transfer N Supports automatic interrupt polling rate mechanism N Supports paired buffering for bulk transfer N Directly addressable memory architecture; memory can be updated on-the-fly ...
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... NXP Semiconductors 3.1 Host/peripheral roles I Mobile phone to/from: N Mobile phone: exchange contact information N Digital still camera: e-mail pictures or upload pictures to the web N MP3 player: upload, download and broadcast music N Mass storage: upload and download files N Scanner: scan business cards I Digital still camera to/from: ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name ISP1362BD LQFP64 ISP1362EE TFBGA64 ISP1362_5 Product data sheet Description plastic low profile quad flat package; 64 leads; body 10 plastic thin fine-pitch ball grid array package; 64 balls; body 6 Rev. 05 — 8 May 2007 ...
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POWER-ON RESET RESET H_SUSPEND/ 33 H_WAKEUP 13 18, 63 D[15: BUS A0 62 INTERFACE A1 28 DACK1 29 DACK2 24 DREQ1 ...
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... DGND D10 13 D11 D12 15 16 D13 Fig 2. Pin configuration LQFP64 Fig 3. Pin configuration TFBGA64 ISP1362_5 Product data sheet ISP1362BD 004aaa050 ball A1 index area ISP1362EE Transparent top view Rev. 05 — 8 May 2007 ISP1362 Single-chip USB OTG Controller ID H_DP2 H_DM2 OTGMODE ...
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... NXP Semiconductors 6.2 Pin description Table 2. Pin description [1] Symbol Pin LQFP64 TFBGA64 DGND DGND D10 12 H2 D11 13 H1 ISP1362_5 Product data sheet Type Description - digital ground I/O bit 2 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance ...
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... NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 D12 15 J1 D13 16 K1 D14 17 K2 D15 18 J3 DGND TEST0 23 K5 DREQ1 24 J6 ISP1362_5 Product data sheet Type Description - supply voltage (3.3 V recommended that you connect a decoupling capacitor of 0.01 F I/O bit 12 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362 ...
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... NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 DREQ2 DGND 27 K7 DACK1 28 J8 DACK2 29 K8 INT1 30 J9 INT2 31 K9 RESET 32 K10 H_SUSPEND/ 33 J10 H_WAKEUP D_SUSPEND D_WAKEUP ISP1362_5 Product data sheet Type Description O DMA request output; when active, it signals the DMA controller that a data transfer is requested by the Peripheral Controller ...
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... NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 H_PSW1 35 H10 H_PSW2 36 G9 DGND 37 G10 CLKOUT F10 H_OC2 41 E10 H_OC1 D10 OTGMODE 45 C10 H_DM2 46 B9 H_DP2 47 B10 ID 48 A10 ISP1362_5 Product data sheet Type Description O connects to the external PMOS switch; required when the external ...
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... NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 OTG_DM1 49 A9 OTG_DP1 50 B8 AGND CP_CAP1 53 A7 CP_CAP2 BUS DD(5V) DGND TEST1 59 A4 TEST2 [1] Symbol names with an overscore (for example, NAME) represent active LOW signals. [2] In OTG mode, this pin is pulled down by an internal resistor. ...
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... NXP Semiconductors 7. Functional description 7.1 On-The-Go (OTG) controller The OTG Controller provides all the control, monitoring and switching functions required in OTG operations. 7.2 Advanced NXP Slave Host Controller The advanced NXP Slave Host Controller is designed for highly optimized USB host functionality. Many advanced features are integrated to fully utilize the USB bandwidth. A number of tasks are performed at the hardware level ...
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... NXP Semiconductors 7.9 GoodLink Indication of a good USB connection is provided through the GoodLink technology (open-drain, maximum current: 4 mA). During enumeration, LED indicators momentarily blink on corresponding to the enumeration traffic of the ISP1362 ports. The LED also blinks on whenever there is valid traffic to the USB ports. In ‘suspend’ mode, the LED is off ...
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... NXP Semiconductors 8.1 Memory organization The buffer memory in the Host Controller uses a multiconfigurable direct addressing architecture. The 4096 bytes Host Controller buffer memory is shared by the ISTL0, ISTL1, INTL and ATL buffers. ISTL0 and ISTL1 are used for isochronous traffic (double buffer), INTL is used for interrupt traffi ...
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... NXP Semiconductors Fig 4. Recommended values of the ISP1362 buffer memory allocation The INTL and ATL buffers use ‘blocked memory management’ scheme to enhance the status and control capability of each and every individual Philips Transfer Descriptor (PTD) structure. The INTL and ATL buffers are further divided into blocks of equal sizes, depending on the value written to the HcATLBlkSize register (ATL) and the HcINTLBlkSize register (INTL) ...
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... NXP Semiconductors Fig 5. A sample snapshot of the ATL or INTL memory management scheme Figure 5 block size of 64 bytes. The HCD may put a PTD with payload size bytes but not more. Depending on the ATL or INTL buffer size ATL blocks and 32 INTL blocks can be allocated. Note that a portion of the ATL or INTL buffer remains unused. This is allowed but can be avoided by choosing the appropriate ATL or INTL buffer size and block size ...
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... NXP Semiconductors Fig 6. A sample snapshot of the ISTL memory management scheme 8.1.2 Memory organization for the Peripheral Controller The ISP1362 Peripheral Controller has a total of 2462 bytes of built-in buffer memory. This buffer memory is multiconfigurable to support the requirements of different applications. The Peripheral Controller buffer memory is divided into 16 areas to be used by control OUT, control IN and 14 programmable endpoints ...
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... NXP Semiconductors Fig 7. Peripheral Controller buffer memory organization The buffer memory is configured by DcEndpointConfiguration Registers (ECRs). Although the control endpoint has a fixed configuration, all 16 endpoints (control OUT, control IN and 14 programmable endpoints) must be configured before the Peripheral Controller internally allocates the buffer. The 14 programmable endpoints can be programmed into sizes ranging from 16 bytes to 1023 bytes, single or double buffering ...
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... NXP Semiconductors Fig 8. PIO interface between a microprocessor and the ISP1362 8.3 DMA mode The ISP1362 also provides DMA mode for external microprocessors to access the internal buffer memory of the ISP1362. The DMA operation enables data to be transferred between the system memory of a microprocessor and the internal buffer memory of the ISP1362 ...
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... NXP Semiconductors 8.4 PIO access to internal control registers Table 5 decoding must combine with the chip select signal (CS) and address lines (A1 and A0). The direction of access of I/O ports, however, is controlled by the RD and WR signals. When RD is LOW, the microprocessor reads data from the data port of the ISP1362 (see Figure 10) ...
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... NXP Semiconductors Fig 11. Access to internal control registers A0/ D[15:0] Fig 12. PIO register access ISP1362_5 Product data sheet CMD/DATA SWITCH host or device 1 command port bus interface 0 data port A0 When the microprocessor accesses the data port. When the microprocessor accesses the command port. Read 16-bit Rev. 05 — ...
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... NXP Semiconductors A0/ D[15:0] Command phase A0/ D[15:0] Command phase Fig 13. PIO access for a 16-bit or 32-bit register The following is a sample code for PIO access to internal control registers: unsigned long read_reg32(unsigned char reg_no) { unsigned int result_l,result_h; unsigned long result; outport(hc_com, reg_no); // Command phase result_l = inport(hc_data) ...
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... NXP Semiconductors result = result_h; result = result<<16; result = result+result_l; return(result); } void write_reg32(unsigned char reg_no, unsigned long data2write) { unsigned int low_word; unsigned int hi_word; low_word=data2write&0x0000FFFF; hi_word=(data2write&0xFFFF0000)>>16; outport(hc_com,reg_no|0x80); // Command phase outport(hc_data,low_word); // Data phase outport(hc_data,hi_word); // Data phase } unsigned int read_reg16(unsigned char reg_no) { unsigned int result ...
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... NXP Semiconductors void Set_DirAddrLen(unsigned int data_length,unsigned int addr) { unsigned long RegData = 0; RegData =(long)(addr&0x7FFF); RegData|=(((long)data_length)<<16); write_reg32(HcDirAddrLen,RegData); } After the proper value is written to the HcDirectAddressLength register, data is accessible from the HcDirectAddressData register (called as HcDirAddr_Port in the following sample code). A sample code to write word_size bytes of data from *w_ptr to the memory ...
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... NXP Semiconductors cnt= outport(hc_data,*(a_ptr+cnt)); // hc_data is system address of HC cnt++; } while(cnt<(word_size)); Remark: The HcTransferCounter register counts the number of bytes even though the transfer is in number of words. Therefore, the transfer counter must be set to word_size 2. Incorrect setting of the HcTransferCounter register may cause the ISP1362 to go into an indeterminate state ...
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... NXP Semiconductors • HcTransferCounter – If DMACounterEnable of the HcDMAConfiguration register is set (that is, the DMA counter is enabled), HcTransferCounter must be set to the number of bytes to be transferred. • HcDMAConfiguration – Read or write DMA (bit 0) – Targeted buffer: ISTL0, ISTL1, ATL and INTL (bits – ...
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... NXP Semiconductors OtgInterruptEnable register OTG_TMR_IE B_SE0_SRP_IE A_SRP_DET_IE OTG_RESUME_IE OTG_SUSPND_IE RMT_CONN_IE B_SESS_VLD_IE A_SESS_VLD_IE B_SESS_END_IE A_VBUS_VLD_IE ID_REG_IE OtgInterrupt register OTG_TMR_TIMEOUT B_SE0_SRP A_SRP_DET OTG_RESUME OTG_SUSPND RMT_CONN_C B_SESS_VLD_C A_SESS_VLD_C B_SESS_END_C A_VBUS_VLD_C ID_REG_C HcInterruptEnable register MIE RHSC FNO HcInterruptStatus register RHSC (OPR group) FNO Fig 14. HC and OTG interrupt logic ...
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... NXP Semiconductors Interrupt level 2 (OPR group) contains six possible interrupt events (recorded in the HcInterruptStatus register). When any of these events occurs, the corresponding bit will be set to logic 1, and if the corresponding bit in the HcInterruptEnable register is also logic 1, the 6-input OR gate will output logic 1. This output is combined with the value of MIE (bit 31 of HcInterruptEnable) using the AND operation and logic 1 output at this AND gate will cause the OPR bit in the Hc PInterrupt register to be set to logic 1 ...
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... NXP Semiconductors The DcMode register (bit 3) is the overall Peripheral Controller interrupt enable. DcHardwareConfiguration determines the following features: • Level-triggered or edge-triggered (bit 1) • Output polarity (bit 0) For details on the interrupt logic in the Peripheral Controller, refer to Control application 8.7.3 Combining INT1 and INT2 In some embedded systems, interrupt inputs to the CPU are a very scarce resource ...
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... NXP Semiconductors 9. Power-On Reset (POR) When V will typically be 800 ns. The pulse is started when V To give a better view of the functionality, dips and t4 to t5. If the dip too short (that is, < 11 s), the internal POR pulse will not react and will remain LOW. The internal POR starts with a HIGH at t0. ...
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... NXP Semiconductors 10. On-The-Go (OTG) Controller 10.1 Introduction OTG is a supplement to the Hi-Speed USB (USB 2.0) specification that augments existing USB peripherals by adding to these peripherals limited host capability to support other targeted USB peripherals primarily targeted at portable devices because it addresses concerns related to such devices, such as a small connector and low power. Non-portable devices (even standard hosts), nevertheless, can also benefi ...
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... NXP Semiconductors If the B-device wants to start a session, it must initiate SRP by ‘data line pulsing’ and ‘V pulsing’. When the A-device detects any of these SRP events, it turns on its V BUS (note that only the A-device is allowed to drive V peripheral, and the A-device assumes the role of a host. The A-device detects that the B-device can support HNP by getting the OTG descriptor from the B-device ...
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... NXP Semiconductors – Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1. • Steps to enable the SRP detection by data line pulsing: – Set A_SEL_SRP (bit 9) of the OtgControl register to logic 1. – Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1. • Steps to disable the SRP detection: – ...
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... NXP Semiconductors HNP request from the B-device. At this point, the B-device becomes a host and asserts bus reset to start using the bus. The B-device must assert the bus reset (that is, SE0) within the time that the A-device turns on its pull-up. 5. When the B-device completes using the bus, it stops all bus activities. Optionally, the B-device may turn on its DP pull-up at this time ...
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... NXP Semiconductors START id | a_bus_req | (a_sess_vld/ & b_conn/) a_wait_vfall drv_vbus/ loc_conn/ loc_sof a_bus_drop a_peripheral drv_vbus loc_conn loc_sof/ b_conn/ & a_set_b_hnp_en id | a_bus_drop | a_aidl_bdis_tmout a_suspend drv_vbus loc_conn/ loc_sof/ Fig 18. Dual-role A-device state diagram ISP1362_5 Product data sheet a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof a_bus_drop | a_wait_bcon_tmout ...
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... NXP Semiconductors Fig 19. Dual-role B-device state diagram 10.4.3 HNP implementation and OTG state machine The OTG state machine is the software behind all the OTG functionality implemented in the microprocessor system that is connected to the ISP1362. The ISP1362 provides all input status, the output control and timers to fully support the state machine transitions in ...
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... NXP Semiconductors 1. Set the polarity and level-triggering or edge-triggering mode of the HcHardwareConfiguration register (bits 1 and 2, default is level-triggered, active LOW). 2. Set the corresponding bits of the OtgInterruptEnable register (bits some of them). 3. Set bit OTG_IRQ_InterruptEnable of the Hc PInterruptEnable register (bit 9). 4. Set bit InterruptPinEnable of the HcHardwareConfiguration register (bit 0). ...
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... NXP Semiconductors Table 7. Capacitance The connection of the external capacitor (C Figure 20. Remark: If the internal charge pump is not used, C Fig 20. External capacitors connection 11. USB Host Controller (HC) 11.1 USB states of the Host Controller The USB Host Controller in the ISP1362 has four USB states: USBOperational, USBReset, USBSuspend and USBResume. These states defi ...
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... NXP Semiconductors USBOperational write USBSuspend write Fig 21. USB Host Controller states of the ISP1362 The USB states are reflected in the HostControllerFunctionalState (HCFS) field of the HcControl register. The HCD is allowed to perform only USB state transitions shown in Figure 21. 11.2 USB traffic generation USB traffic can be generated only when the ISP1362 USB Host Controller is under the USBOperational state. Therefore, the HCD must set the ISP1362 USB HC in the USBOperational state. This is done by setting the HCFS fi ...
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... NXP Semiconductors 9. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. The hexadecimal value of one of the registers must change to 0001 0101h, indicating that a device connection has been detected. 10. Write 32-bit hexadecimal value 0000 0102h into either HcRhPortStatus[1] or HcRhPortStatus[2], depending on the port that is being used. ...
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... NXP Semiconductors structure in the memory buffer will have an offset of 0 bytes and the second PTD structure will have an offset of 40 bytes [sum of the block size (32 bytes) and the PTD header size (8 bytes)]. Because of the fixed block size of the ISP1362 Host Controller, however, even a PTD with 4 bytes of payload will occupy all the 40 bytes in a block. In the isochronous PTD, the Host Controller uses a more fl ...
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... NXP Semiconductors Table 9. Generic PTD structure: bit allocation [1] Bit 7 Byte 0 Byte 1 CompletionCode[3:0] Byte 2 Byte 3 EndpointNumber[3:0] Byte 4 Byte 5 B5[7] B5[6] Byte 6 reserved Byte 7 [1] All reserved bits should be set to logic 0. Table 10. [1] Bit B3[3] B5[6] B5[7] B7[7:0] [1] All reserved bits should be set to logic 0. ...
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... NXP Semiconductors Table 11. Generic PTD structure: bit description Name Status update by HC ActualBytes[9:0] Yes CompletionCode[3:0] Yes Active Yes Toggle Yes MaxPktSize[9:0] No EndpointNumber[3:0] No ISP1362_5 Product data sheet Description This field contains the number of bytes that were transferred for this PTD. 0000 NoError ...
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... NXP Semiconductors Table 11. Generic PTD structure: bit description Name Status update by HC B3[3] Last (PTD) No Speed (low) No TotalBytes[9:0] No B5[6] Ping-Pong No B5[7] Paired No DirToken[1:0] No FunctionAddress[6:0] No B7[7:5] PollingRate No B7[4:0] StartingFrame (interrupt only) B7[7:0] StartingFrame No (ISO only) 11.5 Features of the control and bulk transfer (aperiodic transfer) • ...
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... NXP Semiconductors 11.5.1 Sending a USB device request (Get Descriptor) This section provides an example on how a USB transfer descriptor ‘Get Descriptor’ (commonly used in device enumeration) is used to illustrate the ISP1362 PTD application. To perform this example, make sure the ISP1362 is in the operational state, and then connect a USB device (for example, a USB mouse port ...
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... NXP Semiconductors 11.6 Features of the interrupt transfer • An interrupt transaction is periodically sent out, according to the ‘interrupt polling rate’ as defined in the PTD. • An interrupt transaction causes an interrupt to the CPU only if the transaction is ACK-ed or has error conditions, such as STALL or no respond. An ACK condition occurs if data is received on the IN token or data is sent out on the OUT token. • ...
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... NXP Semiconductors In general applications, you can use a P-channel MOSFET as the power switch for V Connect the 5 V power supply to the source pole of the P-channel MOSFET, V drain pole, and H_PSWn to the gate pole. This voltage drop ( V) across the drain and source poles can be called the overcurrent trip voltage. For the internal overcurrent detection circuit, a voltage comparator has been designed-in, with a nominal voltage threshold ...
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... NXP Semiconductors Fig 24. Using external overcurrent detection circuit 11.8.3 Overcurrent detection circuit using internal charge pump in OTG mode When port 1 is operating in OTG mode, you may choose to use the internal charge pump to provide condition is detected by a drop in V overcurrent condition causes a change in the A_VBUS_VLD bit of the OtgStatus register. ...
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... NXP Semiconductors 11.8.4 Overcurrent detection circuit using external 5 V power source in OTG mode In OTG mode using external 5 V power source for V the same as that for non-OTG mode (see 11.9 ISP1362 Host Controller power management In the ISP1362, the Host Controller and the Peripheral Controller are suspended and woken up individually ...
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... NXP Semiconductors 12.1 Peripheral Controller data transfer operation The following sessions explain how the Peripheral Controller in the ISP1362 handles an IN data transfer and an OUT data transfer data transfer means transfer from the ISP1362 to an external USB host (through the upstream port), and an OUT transfer means transfer from an external USB host to the ISP1362 ...
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... NXP Semiconductors 12.2 Device DMA transfer 12.2.1 DMA for an IN endpoint (internal Peripheral Controller to the external USB host) When the internal DMA handler is enabled and at least one buffer (ping or pong) is free, the DREQ2 line is asserted. The external DMA controller then starts negotiating for control of the bus ...
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... NXP Semiconductors 12.3 Endpoint description 12.3.1 Endpoints with programmable buffer memory size Each USB device is logically composed of several independent endpoints. An endpoint acts as a terminus of a communication flow between the USB host and the USB device. At design time, each endpoint is assigned a unique number (endpoint identifier, see Table 14) ...
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... NXP Semiconductors Table 15. FFOSZ[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Each programmable buffer memory can independently be configured by using its ECR, but the total physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes ...
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... NXP Semiconductors When reset by hardware or by the USB bus occurs, the Peripheral Controller disables all endpoints and clears all ECRs, except the control endpoint that is fixed and always enabled. An endpoint initialization can be done at any time. It is, however, valid only after enumeration. ...
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... NXP Semiconductors 12.4.1 Selecting an endpoint for the DMA transfer The target endpoint for DMA access is selected using bits EPDIX[3:0] of the DcDMAConfiguration register, as shown in is automatically set by the EPDIR bit in the associated ECR, to match the selected endpoint type (OUT endpoint: read; IN endpoint: write). ...
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... NXP Semiconductors The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and HLDA (Hold Acknowledge). The bus operation is controlled by MEMR (Memory Read), MEMW (Memory Write), IOR (I/O Read) and IOW (I/O Write). ...
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... NXP Semiconductors 12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating the bus control lines (MEMR, MEMW, IOR and IOW) and address lines, the CPU resumes the execution of instructions. For a typical bulk transfer, the preceding process is repeated 32 times, once for each word ...
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... NXP Semiconductors 12.4.3.2 Isochronous endpoints A DMA transfer to or from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the DcDMAConfiguration register, see and Table • The DMA transfer completes as programmed in the DcDMACounter register (CNTREN = 1). • An End-Of-Packet (EOP) signal is detected. ...
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... NXP Semiconductors The Peripheral Controller in the ISP1362 will remain in the suspend state for at least 5 ms, before responding to external wake-up events, such as global resume, bus traffic, CS active or LOW pulse on the D_SUSPEND/D_WAKEUP pin. Figure 27 resume operations. USB bus INT2 GOSUSP (bit) D_SUSPEND/D_WAKEUP CS Fig 27 ...
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... NXP Semiconductors 1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, clock signals are routed to all internal circuits of the Peripheral Controller in the ISP1362. 2. The D_SUSPEND/D_WAKEUP pin goes LOW, and the RESUME bit of the DcInterrupt register is set. This will generate an interrupt if bit IERESUME of the DcInterruptEnable register is set ...
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... NXP Semiconductors Table 23. Bit ISP1362_5 Product data sheet OtgControl register: bit description Symbol Description reserved OTG_SE0_ This bit is used by the Host Controller to send SE0 on remote connect — no SE0 sent on remote connect detection 1 — SE0 (bus reset) sent on remote connect detection Remark: This bit is normally set when the B-device goes into the ...
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... NXP Semiconductors Table 23. Bit 13.2 OtgStatus register (R: 67h) Code (Hex): 67 — read only Table 24. OtgStatus register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol reserved Reset - Access - Table 25. Bit ISP1362_5 Product data sheet OtgControl register: bit description Symbol Description DISCHRG_ This bit is for the B-device only. If set, it will enable a pull-down resistor ...
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... NXP Semiconductors Table 25. Bit 13.3 OtgInterrupt register (R/W: 68h/E8h) Code (Hex): 68 — read Code (Hex): E8 — write Table 26. OtgInterrupt register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol OTG_ OTG_ RESUME SUSPND Reset 0 Access R/W R/W ISP1362_5 Product data sheet OtgStatus register: bit description ...
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... NXP Semiconductors Table 27. Bit ISP1362_5 Product data sheet OtgInterrupt register: bit description Symbol Description - reserved OTG_TMR_ This bit is set whenever the OTG timer attains time-out. Writing logic 1 TIMEOUT clears this bit. Writing logic 0 has no effect. 0 — no event 1 — OTG timer time-out B_SE0_SRP This bit is set whenever the device detects more than SE0 ...
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... NXP Semiconductors Table 27. Bit 13.4 OtgInterruptEnable register (R/W: 69h/E9h) Code (Hex): 69 — read Code (Hex): E9 — write Table 28. OtgInterruptEnable register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol OTG_ OTG_ RESUME_ SUSPND_ IE Reset 0 Access R/W R/W Table 29. Bit ISP1362_5 Product data sheet ...
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... NXP Semiconductors Table 29. Bit 13.5 OtgTimer register (R/W: 6Ah/EAh) Code (Hex): 6A — read Code (Hex): EA — write Table 30. OtgTimer register: bit allocation Bit 31 Symbol START_ TMR Reset 0 Access R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W ...
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... NXP Semiconductors Table 31. Bit 13.6 OtgAltTimer register (R/W: 6Ch/ECh) Code (Hex): 6C — read Code (Hex): EC — write Table 32. OtgAltTimer register: bit allocation Bit 31 Symbol START_ TMR Reset 0 Access R/W Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 0 Access ...
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... NXP Semiconductors Table 33. Bit 14. Host Controller registers The Host Controller contains a set of on-chip control registers. These registers can be read or written by the Host Controller Driver (HCD). The operational registers are made compatible to Open Host Controller Interface (OHCI) operational registers. This enables the OHCI HCD to be easily ported to the ISP1362. ...
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... NXP Semiconductors Table 34. Host Controller registers overview Command (Hex) Register Read Write 12 92 HcRhDescriptorA 13 93 HcRhDescriptorB 14 94 HcRhStatus 15 95 HcRhPortStatus[ HcRhPortStatus[ HcHardwareConfiguration 21 A1 HcDMAConfiguration 22 A2 HcTransferCounter PInterrupt PInterruptEnable 27 N/A HcChipID 28 A8 HcScratch N/A A9 HcSoftwareReset 2C AC HcBufferStatus 32 B2 HcDirectAddressLength 45 C5 ...
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... NXP Semiconductors 14.1 HC control and status registers 14.1.1 HcRevision register (R: 00h) The bit allocation of the HcRevision register is given in Code (Hex): 00 — read only Table 35. HcRevision register: bit allocation Bit 31 Symbol Reset - Access - Bit 23 Symbol Reset - Access - Bit 15 Symbol Reset - Access - Bit ...
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... NXP Semiconductors Bit 23 Symbol Reset - Access - Bit 15 Symbol Reset - Access - Bit 7 Symbol HCFS[1:0] Reset 0 Access R/W R/W Table 38. Bit ISP1362_5 Product data sheet reserved - - - - - - reserved - - - - - - HcControl register: bit description Symbol Description - reserved RWE RemoteWakeupEnable: This bit is used by the HCD to enable or disable the remote wake-up feature on detecting upstream resume signaling ...
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... NXP Semiconductors 14.1.3 HcCommandStatus register (R/W: 02h/82h) The HcCommandStatus register bytes register, and the bit allocation is given in Table 39. This register is used by the Host Controller to receive commands issued by the HCD, and it also reflects the current status of the Host Controller. To the HCD, it appears ‘ ...
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... NXP Semiconductors Table 40. Bit 14.1.4 HcInterruptStatus register (R/W: 03h/83h) This register (bit allocation: hardware interrupts. When an event occurs, the Host Controller sets the corresponding bit in this register. When a bit is set, a hardware interrupt is generated if the corresponding interrupt is enabled in the HcInterruptEnable register (see MasterInterruptEnable (MIE) bit is set. The HCD must write logic 1 to the specifi ...
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... NXP Semiconductors Table 42. Bit 14.1.5 HcInterruptEnable register (R/W: 04h/84h) Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. When the following three conditions occur: • A bit is set in the HcInterruptStatus register. ...
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... NXP Semiconductors Bit 23 Symbol Reset - Access - Bit 15 Symbol Reset - Access - Bit 7 Symbol reserved RHSC Reset - Access - R/W Table 44. Bit 14.1.6 HcInterruptDisable register (R/W: 05h/85h) Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register ...
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... NXP Semiconductors Table 45. HcInterruptDisable register: bit allocation Bit 31 Symbol MIE Reset 0 Access R/W Bit 23 Symbol Reset - Access - Bit 15 Symbol Reset - Access - Bit 7 Symbol reserved RHSC Reset - Access - R/W Table 46. Bit 14.2 HC frame counter registers 14.2.1 HcFmInterval register (R/W: 0Dh/8Dh) The HcFmInterval register (bit allocation: the bit time interval in a frame between two consecutive SOFs ...
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... NXP Semiconductors adjustments on FrameInterval by writing a new value over the present one at each SOF. This provides the programmability necessary for the Host Controller to synchronize with an external clocking resource and to adjust any unknown local clock offset. Code (Hex): 0D — read Code (Hex): 8D — write Table 47 ...
Page 79
... NXP Semiconductors Code (Hex): 8E — write Table 49. HcFmRemaining register: bit allocation Bit 31 Symbol FRT Reset 0 Access R/W Bit 23 Symbol Reset - Access - Bit 15 Symbol reserved Reset - Access - Bit 7 Symbol Reset 0 Access R/W R/W Table 50. Bit 14.2.3 HcFmNumber register (R/W: 0Fh/8Fh) The HcFmNumber register is a 16-bit counter, and the bit allocation is given in provides a timing reference for events happening in the Host Controller and the HCD. The HCD may use the 16-bit value specifi ...
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... NXP Semiconductors Table 51. HcFmNumber register: bit allocation Bit 31 Symbol Reset - Access - Bit 23 Symbol Reset - Access - Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 0 Access R Table 52. Bit 14.2.4 HcLSThreshold register (R/W: 11h/91h) The HcLSThreshold register contains an 11-bit value. This value is used by the Host Controller to determine whether to start a transfer of a maximum of 8 bytes LS packet before the EOF ...
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... NXP Semiconductors Bit 15 Symbol Reset - Access - Bit 7 Symbol Reset 0 Access R/W R/W Table 54. Bit 14.3 HC root hub registers All registers included in this partition are dedicated to the USB root hub, which is an integral part of the Host Controller although it is functionally a separate entity. The HCD emulates USB Driver (USBD) accesses to the root hub by using a register interface. The HCD maintains many USB-defi ...
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... NXP Semiconductors Code (Hex): 92 — write Table 55. HcRhDescriptorA register: bit description Bit 31 Symbol Reset 1 Access R/W R/W Bit 23 Symbol Reset - Access - Bit 15 Symbol reserved Reset - Access - Bit 7 Symbol Reset - Access - Table 56. Bit ISP1362_5 Product data sheet POTPGT[7: R/W R reserved - - - - - ...
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... NXP Semiconductors Table 56. Bit 14.3.2 HcRhDescriptorB register (R/W: 13h/93h) The HcRhDescriptorB register is the second of two registers describing the characteristics of the root hub. These fields are written during initialization to correspond to the system implementation. Code (Hex): 13 — read Code (Hex): 93 — write Table 57. ...
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... NXP Semiconductors Table 58. Bit 14.3.3 HcRhStatus register (R/W: 14h/94h) The HcRhStatus register is divided into two parts. The lower word of a double-word represents the hub status field and the upper word represents the hub status change field. Reserved bits should always be written as logic 0. See register. Code (Hex): 14 — ...
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... NXP Semiconductors Table 60. Bit 14.3.4 HcRhPortStatus[1:2] register (R/W [1]: 15h/95h; [2]: 16h/96h) The HcRhPortStatus[1:2] register is used to control and report port events on a per-port basis. NumberofDownstreamPort represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word refl ...
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... NXP Semiconductors Bit 23 Symbol reserved Reset - Access - Bit 15 Symbol Reset - Access - Bit 7 Symbol reserved Reset - Access - Table 62. Bit ISP1362_5 Product data sheet PRSC - - R reserved - - - - - - PRS - - R/W HcRhPortStatus[1:2] register: bit description Symbol Description - reserved PRSC PortResetStatusChange: This bit is set at the end of the 10 ms port reset signal ...
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... NXP Semiconductors Table 62. Bit ISP1362_5 Product data sheet HcRhPortStatus[1:2] register: bit description Symbol Description CSC ConnectStatusChange: This bit is set whenever a connect or disconnect event occurs. The HCD writes logic 1 to clear this bit. Writing logic 0 has no effect. If CurrentConnectStatus (CCS) is cleared when a SetPortReset, SetPortEnable or SetPortSuspend write occurs, this bit is set to force the driver to re-evaluate the connection status because these writes should not occur if the port is disconnected ...
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... NXP Semiconductors Table 62. Bit ISP1362_5 Product data sheet HcRhPortStatus[1:2] register: bit description Symbol Description PRS On read PortResetStatus: When this bit is set by a write to SetPortReset, port reset signaling is asserted. When reset is completed, this bit is cleared when PortResetStatusChange (PRSC) is set. This bit cannot be set if CurrentConnectStatus (CCS) is cleared. ...
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... NXP Semiconductors Table 62. Bit 1 0 14.4 HC DMA and interrupt control registers 14.4.1 HcHardwareConfiguration register (R/W: 20h/A0h) The bit allocation of the HcHardwareConfiguration register is given in Code (Hex): 20 — read Code (Hex): A0 — write Table 63. HcHardwareConfiguration register: bit allocation Bit 15 Symbol ...
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... NXP Semiconductors Table 64. Bit ISP1362_5 Product data sheet HcHardwareConfiguration register: bit description Symbol Description DisableSuspend_Wakeup This bit when set to logic 1 disables the function of the D_SUSPEND/D_WAKEUP and H_SUSPEND/H_WAKEUP pins. Therefore, these pins will always remain HIGH and pulling them LOW does not wake-up the Host Controller and the Peripheral Controller ...
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... NXP Semiconductors Table 64. Bit 14.4.2 HcDMAConfiguration register (R/W: 21h/A1h) Table 65 Code (Hex): 21 — read Code (Hex): A1 — write Table 65. HcDMAConfiguration register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol DMACounter Enable Reset 0 Access R/W R/W Table 66. Bit ISP1362_5 Product data sheet HcHardwareConfi ...
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... NXP Semiconductors Table 66. Bit Table 67. Bit 14.4.3 HcTransferCounter register (R/W: 22h/A2h) Regardless of PIO or DMA data transfer modes, this register is used to initialize the number of bytes to be transferred to or from the ISTL, INTL or ATL buffer RAM. For the count value loaded in the register to take effect, the HCD is required to set bit 7 of the HcDMAConfi ...
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... NXP Semiconductors Table 69. Hc PInterrupt register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol INTL_IRQ ClkReady Reset 0 Access R/W R/W Table 70. Bit ISP1362_5 Product data sheet reserved - - - - - - OPR_Reg Suspended R/W R/W Hc PInterrupt register: bit description Symbol Description - reserved OTG_IRQ 0 — no event 1 — ...
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... NXP Semiconductors Table 70. Bit 14.4.5 Hc PInterruptEnable register (R/W: 25h/A5h) Bits this register are the same as those in the Hc PInterrupt register. The bits in this register are used together with bit 0 of the HcHardwareConfiguration register to enable or disable the bits in the Hc PInterrupt register. At power-on, all the bits in this register are masked with logic 0. This means no interrupt request output on interrupt pin INT1 can be generated ...
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... NXP Semiconductors Table 72. Bit 14.5 HC miscellaneous registers 14.5.1 HcChipID register (R: 27h) This register contains the ID of the ISP1362. The upper byte identifies the product name (here 36h stands for the ISP1362). The lower byte indicates the revision number of the product, including engineering samples. ...
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... NXP Semiconductors Table 74. HcScratch register: bit description Bit Symbol Scratch[15:0] 14.5.3 HcSoftwareReset register (W: A9h) This register provides a means for the software reset of the Host Controller. To reset the Host Controller, the HCD must write a reset value of F6h to this register. On receiving this reset value, the Host Controller resets all the Host Controller and OTG registers, except its buffer memory ...
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... NXP Semiconductors Table 77. Bit 14.6.2 HcDirectAddressLength register (R/W: 32h/B2h) The HcDirectAddressLength register is used for direct addressing of the ISTL, INTL or ATL buffers. This register specifies the starting address of the buffer and byte count of data to be addressed. Therefore, it allows the programmer to randomly access the buffer. ...
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... NXP Semiconductors Bit 7 Symbol Reset 0 Access R/W R/W Table 79. Bit 14.6.3 HcDirectAddressData register (R/W: 45h/C5h) This is a data port for the HCD to access the ISTL, INTL or ATL buffers under direct addressing mode. Code (Hex): 45 — read Code (Hex): C5 — write Table 80. ...
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... NXP Semiconductors Table 82. HcISTL0BufferPort register: bit description Bit Symbol Access DataWord[15:0] R/W The HCD is first required to initialize the HcTransferCounter register with the byte count to be transferred and check the HcBufferStatus register. The HCD then sends the command (40h to read from the ISTL0 buffer, and C0h to write to the ISTL0 buffer) to the Host Controller through the I/O port of the microprocessor ...
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... NXP Semiconductors Bit 7 Symbol Reset - Access - Table 85. Bit 14.8 Interrupt transfer registers 14.8.1 HcINTLBufferSize register (R/W: 33h/B3h) This register allows you to allocate the size of the INTL buffer to be used for interrupt transactions. The default value of the buffer size is set to 128 bytes, and the maximum allowable allocated size is 4096 bytes. Code (Hex): 33 — ...
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... NXP Semiconductors 14.8.3 HcINTLBlkSize register (R/W: 53h/D3h) The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks so that the Host Controller can skip the current PTD and proceed to process the next PTD easily. The block size of the INTL buffer is required to be specified in this register and must be a multiple of 8 bytes ...
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... NXP Semiconductors PTD if the HCD has reset its corresponding skipped bit to logic 0. Clearing the corresponding bit in the HcINTLPTDSkipMap register when there is no valid data in the block will cause unpredictable behavior of the Host Controller. Code (Hex): 18 — read Code (Hex): 98 — write Table 91 ...
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... NXP Semiconductors Table 94. Bit 14.9 Control and bulk transfer (aperiodic transfer) registers 14.9.1 HcATLBufferSize register (R/W: 34h/B4h) This register allows you to allocate the size of the ATL buffer to be used for aperiodic transactions. The default value of the buffer size is set to 512 bytes, and the maximum allowable allocated size is 4096 bytes ...
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... NXP Semiconductors Code (Hex): 54 — read Code (Hex): D4 — write Table 97. HcATLBlkSize register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol Reset 0 Access R/W R/W Table 98. Bit 14.9.4 HcATLPTDDoneMap register (R: 1Bh) This is a 32-bit register. The bit description of the register is given in the register represents the processing status of a PTD. Bit 0 of the register represents the fi ...
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... NXP Semiconductors Table 100. HcATLPTDSkipMap register: bit description Bit Symbol Access SkipBits R/W [31:0] 14.9.6 HcATLLastPTD register (R/W: 1Dh/9Dh) This is a 32-bit register. register represents the first PTD stored in the ATL buffer, bit 1 represents the second PTD stored in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an indication to the Host Controller that its corresponding PTD is the last PTD stored in the ATL buffer ...
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... NXP Semiconductors 14.9.8 HcATLPTDDoneThresholdCount register (R/W: 51h/D1h) This register specifies the number of ATL PTDs to be done to trigger an ATL interrupt. If set to 08h, the Host Controller will trigger the ATL interrupt (in the Hc PInterrupt register) once every eight ATL PTDs are done. Remark: Do not write 0000h to this register. ...
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... NXP Semiconductors Table 107. HcATLPTDDoneThresholdTimeOut register: bit description Bit 15. Peripheral Controller registers The functions and registers of the Peripheral Controller are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and registers is given in A complete access consists of two phases: 1 ...
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... NXP Semiconductors Table 108. Peripheral Controller command and register overview Name Write or read DcInterruptEnable register Write or read DMA configuration Write or read DMA counter Reset device Data flow commands Write control OUT buffer Write control IN buffer Write endpoint n buffer ( 14) Read control OUT buffer ...
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... NXP Semiconductors Table 108. Peripheral Controller command and register overview Name General commands Read control OUT error code Read control IN error code Read endpoint n error code ( 14) Unlock device Write or read DcScratch register Read frame number Read chip ID Read DcInterrupt register [1] With N representing the number of bytes, the number of words for 16-bit bus width is divided by 2. ...
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... NXP Semiconductors Table 109. DcEndpointConfiguration register: bit allocation Bit 7 Symbol FIFOEN EPDIR Reset 0 Access R/W R/W Table 110. DcEndpointConfiguration register: bit description Bit 15.1.2 DcAddress register (R/W: B7h/B6h) This command is used to set the USB assigned address in the DcAddress register and enable the USB device ...
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... NXP Semiconductors Code (Hex): B8/B9 — write or read DcMode register Transaction — write or read 1 byte (code or data) Table 113. DcMode register: bit allocation Bit 7 Symbol reserved [1] Reset 1 Access R/W R/W [1] Unchanged by a bus reset. Table 114. DcMode register: bit description Bit ...
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... NXP Semiconductors Bit 7 Symbol DAKOLY DRQPOL Reset 0 Access R/W R/W Table 116. DcHardwareConfiguration register: bit description Bit 15.1.5 DcInterruptEnable register (R/W: C3h/C2h) This command is used to individually enable or disable interrupts from all endpoints, as well as interrupts caused by events on the USB bus (SOF, EOT, suspend, resume, reset). ...
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... NXP Semiconductors The command accesses the DcInterruptEnable register, which consists of 4 bytes. The bit allocation is given in Code (Hex): C2/C3 — write or read DcInterruptEnable register Transaction — write or read 4 bytes (code or data) Table 117. DcInterruptEnable register: bit allocation Bit 31 Symbol Reset - Access ...
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... NXP Semiconductors Table 118. DcInterruptEnable register: bit description Bit 15.1.6 DcDMAConfiguration (R/W: F1h/F0h) This command defines the DMA configuration of the Peripheral Controller, and enables or disables DMA transfers. The command accesses the DcDMAConfiguration register, which consists of two bytes. The bit allocation is given in bit DMAEN (DMA disabled), all other bits remain unchanged. Code (Hex): F0/F1 — ...
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... NXP Semiconductors Table 120. DcDMAConfiguration register: bit description Bit 15.1.7 DcDMACounter register (R/W: F3h/F2h) This command accesses the DcDMACounter register, which consists of two bytes. The bit allocation is given in transfer. Reading the register returns the number of remaining bytes in the current transfer. A bus reset will not change programmed bit values. ...
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... NXP Semiconductors 15.2 Data flow commands Data flow commands are used to manage data transmission between USB endpoints and the system microprocessor. Much of the data flow is initiated using an interrupt to the microprocessor. Data flow commands are used to access endpoints and determine whether the endpoint buffer memory contains valid data. ...
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... NXP Semiconductors Table 124. Example of endpoint buffer memory access A0 HIGH LOW LOW LOW … Remark: There is no protection against writing or reading past a buffer’s boundary, against writing into an OUT buffer or reading from an IN buffer. Any of these actions can cause an incorrect operation. Data residing in an OUT buffer is only meaningful after a successful transaction ...
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... NXP Semiconductors Table 126. DcEndpointStatus register: bit description Bit 15.2.3 Stall endpoint or unstall endpoint (40h to 4Fh/80h to 8Fh) These commands are used to stall or unstall an endpoint. The commands modify the content of the DcEndpointStatus register (see A stalled control endpoint is automatically unstalled when it receives a set-up token, regardless of the packet content ...
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... NXP Semiconductors Code (Hex): 70 — clear endpoint buffer (control OUT, endpoints 1 to 14) Transaction — none (code only) 15.2.6 DcEndpointStatusImage register (D0h to DFh) This command is used to check the status of the selected endpoint buffer memory, without clearing any status or interrupt bits. The command accesses the DcEndpointStatusImage register, which contains a copy of the DcEndpointStatus register ...
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... NXP Semiconductors 15.3 General commands 15.3.1 Read endpoint error code (R: A0h to AFh) This command returns the status of the last transaction of the selected endpoint, as stored in the DcErrorCode register. Each new transaction overwrites the previous status information. The bit allocation of the DcErrorCode register is shown in Code (Hex — ...
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... NXP Semiconductors 15.3.2 Unlock Device (B0h) This command unlocks the Peripheral Controller from write-protection mode after a ‘resume’. In the ‘suspend’ state, all registers and buffer memory are write-protected to prevent data corruption by external devices during a ‘resume’. Also, the register access to read is possible only after the ‘ ...
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... NXP Semiconductors Table 135. DcScratch Information register: bit description Bit 15.3.4 DcFrameNumber register (R: B4h) This command returns the frame number of the last successfully received SOF followed by reading one word from the DcFrameNumber register, containing the frame number. The DcFrameNumber register is shown in Remark: After a bus reset, the value of the DcFrameNumber register is undefi ...
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... NXP Semiconductors Table 139. DcChipID register: bit allocation Bit 15 14 Symbol Reset 0 0 Access R R Bit 7 6 Symbol Reset 0 0 Access R R Table 140. DcChipID register: bit description Bit 15.3.6 DcInterrupt register (R: C0h) This command indicates the sources of interrupts as stored in the 4 bytes DcInterrupt register ...
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... NXP Semiconductors Table 142. DcInterrupt register: bit description Bit ISP1362_5 Product data sheet Symbol Description - reserved EP14 to EP1 Logic 1 indicates the interrupt source(s): endpoints EP0IN Logic 1 indicates the interrupt source: control IN endpoint. EP0OUT Logic 1 indicates the interrupt source: control OUT endpoint. ...
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... NXP Semiconductors 16. Limiting values Table 143. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I I latch-up current lu V electrostatic discharge voltage esd T storage temperature stg [1] Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor (Human Body Model). ...
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... NXP Semiconductors 18. Static characteristics Table 145. Static characteristics: supply pins 3.6 V; GND = Symbol Parameter I operating supply current for CC(HC) the Host Controller I operating supply current for CC(DC) the Peripheral Controller I operating supply current for CC(HC+DC) the host and the device ...
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... NXP Semiconductors Table 147. Static characteristics: analog I/O pins (D 3 3.6 V; GND = Symbol Parameter Input levels V differential input sensitivity DI V differential common mode CM voltage V LOW-level input voltage IL V HIGH-level input voltage IH Output levels V LOW-level output voltage OL V HIGH-level output voltage OH Leakage current ...
Page 128
... NXP Semiconductors Table 148. Static characteristics: charge pump 3.6 V; GND = Symbol Parameter I suspend supply current for CC(cp)(susp) charge pump I operating supply current in CC(cp) charge pump mode V V valid threshold th(VBUS_VLD) BUS V V session end threshold th(SESS_END) BUS V V session end hysteresis ...
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... NXP Semiconductors V BUS (V) Fig 29. Output voltage as a function of load current ISP1362_5 Product data sheet 5 3 3.3 V 3.0 V 5.0 4.8 4 charge pump capacitor. Rev. 05 — 8 May 2007 ISP1362 Single-chip USB OTG Controller 001aaf830 (mA) LOAD © NXP B.V. 2007. All rights reserved. 128 of 152 ...
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... NXP Semiconductors 19. Dynamic characteristics Table 149. Dynamic characteristics 3.6 V; GND = Symbol Parameter Reset t pulse width on input RESET W(RESET) Crystal oscillator f crystal frequency xtal R series resistance S C load capacitance LOAD External clock input J external clock jitter t clock duty cycle DUTY t rise time ...
Page 131
... NXP Semiconductors Table 151. Dynamic characteristics: charge pump 3.6 V; GND = Symbol Parameter t V pulsing time VBUS(PULSE) BUS t V pull-down time VBUS(VALID_dly) BUS V output ripple with constant RIPPLE load 19.1 Programmed I/O timing • If you are accessing only the Host Controller, then the Host Controller programmed I/O timing applies. • ...
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... NXP Semiconductors 15 data D [ 15:0 ] valid Fig 30. Host Controller programmed interface timing 19.1.2 Peripheral Controller programmed I/O timing Table 153. Dynamic characteristics: Peripheral Controller programmed interface timing 3.6 V; GND = Symbol Parameter Read timing (see Figure 31) t address hold time after RD HIGH ...
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... NXP Semiconductors Table 153. Dynamic characteristics: Peripheral Controller programmed interface timing 3.6 V; GND = Symbol Parameter t chip deselect time after WR HIGH WHSH t data set-up time before WR HIGH DVWH t data hold time after WR HIGH WHDZ [1] In the command to data phase, the minimum value of the write command to the read data or write data cycle time must be 205 ns. ...
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... NXP Semiconductors A0 (2) CS/DACK2 WR t DVWH D[15:0] (1) For t , both CS and WR must be de-asserted. SHWL (2) Programmable polarity: shown as active LOW. Fig 32. Peripheral Controller programmed interface write timing (I/O and 8237 compatible DMA) 19.2 DMA timing 19.2.1 Host Controller single-cycle DMA timing Table 154. Dynamic characteristics: Host Controller single-cycle DMA timing 3.6 V ...
Page 135
... NXP Semiconductors DREQ1 DACK1 D [ 15:0 ] (read 15:0 ] (write Fig 33. Host Controller single-cycle DMA timing 19.2.2 Host Controller burst mode DMA timing Table 155. Dynamic characteristics: Host Controller burst mode DMA timing 3.6 V; GND = Symbol Parameter Read/write timing (for 4-cycle and 8-cycle burst mode) ...
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... NXP Semiconductors DREQ1 t RHSH t RHAL DACK1 Fig 34. Host Controller burst mode DMA timing 19.2.3 Peripheral Controller single-cycle DMA timing (8237 mode) Table 156. Dynamic characteristics: Peripheral Controller single-cycle DMA timing (8237 mode 3 3.6 V; GND = Symbol Parameter t DREQ2 off after DACK2 on ASRP ...
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... NXP Semiconductors DREQ2 (1) DACK2 DATA (1) Programmable polarity: shown as active LOW. Fig 36. Peripheral Controller single-cycle DMA read timing in DACK-only mode 19.2.5 Peripheral Controller single-cycle DMA write timing in DACK-only mode Table 158. Dynamic characteristics: Peripheral Controller single-cycle DMA write timing in DACK-only mode 3.6 V; GND = ...
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... NXP Semiconductors 19.2.6 Peripheral Controller burst mode DMA timing Table 159. Dynamic characteristics: Peripheral Controller burst mode DMA timing 3.6 V; GND = Symbol Parameter t input RD/WR HIGH after DREQ on RSIH t DREQ off after input RD/WR LOW ILRP t DACK off after input RD/WR HIGH ...
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... NXP Semiconductors 20. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 0.8 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.25 0.85 0.35 mm 1.1 0.15 0.75 0.25 OUTLINE VERSION IEC SOT543 Fig 40. Package outline SOT543-1 (TFBGA64) ...
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... NXP Semiconductors 21. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 21.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 21.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 41. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 22. Abbreviations Table 162. Abbreviations Acronym ACK ASIC ATL ATX CMOS CRC DMA DSC ED EHCI ...
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... NXP Semiconductors Table 162. Abbreviations Acronym HNP INTL IS ISO ISR ISTL LS MOSFET MSB NAK OHCI OPR OTG PDA PID PIO PLL PMOS POR PORP POST PTD RISC SIE SOF SRP TD USB USBD 23. References [1] On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a [2] Universal Serial Bus Specifi ...
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... Release date ISP1362_5 20070508 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 2 • Table 2 “Pin • ...
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... NXP Semiconductors Table 163. Revision history …continued Document ID Release date ISP1362-04 20041224 (9397 750 13957) ISP1362-03 20040106 (9397 750 12337) ISP1362-02 20030219 (9397 750 10767) ISP1362-01 20021120 (9397 750 10087) ISP1362_5 Product data sheet Data sheet status Change notice Product data ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 27. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 3. Bus access priority table for the ISP1362 . . . .13 Table 4. Buffer memory areas and their applications . .14 Table 5. I/O port addressing . . . . . . . . . . . . . . . . . . . . .20 Table 6. Registers used in addressing modes . . . . . . . .25 Table 7. Recommended capacitor values . . . . . . . . . . .38 Table 8. Port 1 function . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 9. ...
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... NXP Semiconductors Table 91. HcINTLPTDSkipMap register: bit description 101 Table 92. HcINTLLastPTD register: bit description . . . .101 Table 93. HcINTLCurrentActivePTD register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .101 Table 94. HcINTLCurrentActivePTD register: bit description . . . . . . . . . . . . . . . . . . . . . . . .102 Table 95. HcATLBufferSize register: bit description . . .102 Table 96. HcATLBufferPort register: bit description . . . .102 Table 97. HcATLBlkSize register: bit allocation . . . . . . .103 Table 98 ...
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... NXP Semiconductors 28. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 2. Pin configuration LQFP64 . . . . . . . . . . . . . . . . . . .6 Fig 3. Pin configuration TFBGA64 . . . . . . . . . . . . . . . . . .6 Fig 4. Recommended values of the ISP1362 buffer memory allocation . . . . . . . . . . . . . . . . . . . . . . . .15 Fig 5. A sample snapshot of the ATL or INTL memory management scheme . . . . . . . . . . . . . . . . . . . . .16 Fig 6. A sample snapshot of the ISTL memory management scheme ...
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... NXP Semiconductors 29. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 Host/peripheral roles Ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 12 7.1 On-The-Go (OTG) controller 7.2 Advanced NXP Slave Host Controller 7.3 NXP Peripheral Controller ...
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... NXP Semiconductors 12.3 Endpoint description . . . . . . . . . . . . . . . . . . . . 52 12.3.1 Endpoints with programmable buffer memory size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.3.2 Endpoint access . . . . . . . . . . . . . . . . . . . . . . . 52 12.3.3 Endpoint buffer memory size . . . . . . . . . . . . . 52 12.3.4 Endpoint initialization . . . . . . . . . . . . . . . . . . . 53 12.3.5 Endpoint I/O mode access . . . . . . . . . . . . . . . 54 12.3.6 Special actions on control endpoints . . . . . . . 54 12.4 Peripheral Controller DMA transfer . . . . . . . . . 54 12.4.1 Selecting an endpoint for the DMA transfer . . 55 12 ...
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... NXP Semiconductors 15.2.1 Write or read endpoint buffer (R/W: 10h,12h to 1Fh/01h to 0Fh 115 15.2.2 Read endpoint status (R: 50h to 5Fh 116 15.2.3 Stall endpoint or unstall endpoint (40h to 4Fh/80h to 8Fh 117 15.2.4 Validate endpoint buffer (61h to 6Fh 117 15.2.5 Clear endpoint buffer (70h, 72h to 7Fh 117 15 ...