ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 105

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 100. Mode register (address 020Ch) bit allocation
[1]
ISP1761_4
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
10.5.2 Mode register
CLKAON
R/W
R/W
15
0
0
7
0
0
Table 99.
This register consists of 2 bytes (bit allocation: see
The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft
reset and clock signals.
Table 101. Mode register (address 020Ch) bit description
Bit
7
6 to 0
Bit
15 to 10
9
8
7
SNDRSU
R/W
R/W
14
0
0
6
0
0
Symbol
-
DMACLKON
VBUSSTAT
CLKAON
Address register (address 0200h) bit description
Symbol
DEVEN
DEVADDR[6:0]
GOSUSP
R/W
R/W
13
0
0
5
0
0
reserved
Rev. 04 — 5 March 2007
Description
reserved
DMA Clock On:
1 — Supply clock to the DMA circuit.
0 — Power saving mode. The DMA circuit will stop completely to save
power.
V
Clock Always On:
1 — Enable the Clock-Always-On feature
0 — Disable the Clock-Always-On feature
When the Clock-Always-On feature is disabled, a GOSUSP event can
stop the clock. The clock is stopped after a delay of approximately 2 ms.
Therefore, the Peripheral Controller will consume less power.
If the Clock-Always-On feature is enabled, clocks are always running
and the GOSUSP event is unable to stop the clock while the Peripheral
Controller enters the suspend state.
BUS
Description
Device Enable: Logic 1 enables the device. The device will not
respond to the host, unless this bit is set.
Device Address: This field specifies the USB device peripheral.
SFRESET
Status: This bit reflects the V
[1]
R/W
R/W
12
0
0
4
0
0
GLINTENA
unchanged
R/W
R/W
11
0
0
3
0
Table
WKUPCS
BUS
R/W
R/W
10
100).
0
0
2
0
0
Hi-Speed USB OTG controller
pin status.
DMACLK
R/W
R/W
ON
9
0
0
1
0
0
© NXP B.V. 2007. All rights reserved.
reserved
ISP1761
VBUSSTAT
unchanged
[1]
105 of 163
R/W
R/W
8
0
0
0
0