ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 114

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 119. Endpoint MaxPacketSize register (address 0204h) bit allocation
[1]
ISP1761_4
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
10.6.6 Endpoint MaxPacketSize register
10.6.7 Endpoint Type register
R/W
R/W
15
0
0
7
0
0
This register determines the maximum packet size for all endpoints, except control 0. The
register contains 2 bytes, and the bit allocation is given in
Each time the register is written, the Buffer Length register of the corresponding endpoint
is re-initialized to the FFOSZ field value. NTRANS bits control the number of transactions
allowed in a single micro frame for high-speed isochronous and interrupt endpoints only.
Table 120. Endpoint MaxPacketSize register (address 0204h) bit description
The ISP1761 supports all the transfers given in
Rev.
Each programmable FIFO can be independently configured using its Endpoint
MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN
plus OUT), including set-up token buffer, control IN and control OUT, must not exceed
8192 bytes.
This register sets the endpoint type of the indexed endpoint: isochronous, bulk or
interrupt. It also serves to enable the endpoint and configure it for double buffering.
Automatic generation of an empty packet for a zero-length TX buffer can be disabled using
bit NOEMPKT. The register contains 2 bytes. See
Bit
15 to 13
12 to 11
10 to 0
reserved
2.0”.
R/W
R/W
14
0
0
6
0
0
Symbol
-
NTRANS[1:0]
FFOSZ[10:0]
[1]
R/W
R/W
13
0
0
5
0
0
Rev. 04 — 5 March 2007
Description
reserved
Number of Transactions: HS mode only.
00 — One packet per micro frame
01 — Two packets per micro frame
10 — Three packets per micro frame
11 — reserved
These bits are applicable only for isochronous or interrupt
transactions.
FIFO Size: Sets the FIFO size, in bytes, for the indexed endpoint.
Applies to both high-speed and full-speed operations.
R/W
R/W
12
0
0
4
0
0
NTRANS[1:0]
FFOSZ[7:0]
R/W
R/W
11
0
0
3
0
0
Ref. 1 “Universal Serial Bus Specification
Table
R/W
R/W
121.
10
0
0
2
0
0
Hi-Speed USB OTG controller
Table
119.
FFOSZ[10:8]
R/W
R/W
9
0
0
1
0
0
© NXP B.V. 2007. All rights reserved.
ISP1761
114 of 163
R/W
R/W
8
0
0
0
0
0