ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 115

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 121. Endpoint Type register (address 0208h) bit allocation
[1]
ISP1761_4
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
10.7 DMA registers
R/W
R/W
15
0
0
7
0
0
Table 122. Endpoint Type register (address 0208h) bit description
The Generic DMA (GDMA) transfer can be done by writing the proper opcode in the DMA
Command register. The control bits are given in
GDMA read or write (opcode = 00h/01h) for Generic DMA slave mode
The GDMA (slave) can operate in counter mode. RD_N and WR_N are DMA data strobe
signals. These signals are also used as data strobe signals during the PIO access. An
internal multiplex will redirect these signals to the DMA Controller for the DMA transfer or
to registers for the PIO access.
Bit
15 to 5
4
3
2
1 to 0
reserved
R/W
R/W
14
0
0
6
0
0
Symbol
-
NOEMPKT
ENABLE
DBLBUF
ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type as follows.
[1]
R/W
R/W
13
0
0
5
0
0
Rev. 04 — 5 March 2007
Description
reserved
No Empty Packet: Logic 0 causes the ISP1761 to return a null length
packet for the IN token after the DMA IN transfer is complete. Set to
logic 1 to disable the generation of the null length packet.
Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint.
The memory size is allocated as specified in the Endpoint
MaxPacketSize register. Logic 0 disables the FIFO.
Remark: Stalling a data endpoint will confuse the Data Toggle bit on the
stalled endpoint because the internal logic picks up from where it has
stalled. Therefore, the Data Toggle bit must be reset by disabling and
re-enabling the corresponding endpoint (by setting bit ENABLE to
logic 0, followed by logic 1 in the Endpoint Type register) to reset the
PID.
Double Buffering: Logic 1 enables double buffering for the indexed
endpoint. Logic 0 disables double buffering.
00 — Not used
01 — Isochronous
10 — Bulk
11 — Interrupt
NOEMPKT
R/W
R/W
12
0
0
4
0
0
reserved
ENABLE
[1]
R/W
R/W
11
0
0
3
0
0
Table
DBLBUF
123.
R/W
R/W
10
0
0
2
0
0
Hi-Speed USB OTG controller
R/W
R/W
9
0
0
1
ENDPTYP[1:0]
0
0
© NXP B.V. 2007. All rights reserved.
ISP1761
115 of 163
R/W
R/W
8
0
0
0
0
0