ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 116

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 124. DMA Command register (address 0230h) bit allocation
ISP1761_4
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
10.7.1 DMA Command register
W
7
1
1
In counter mode, the DIS_XFER_CNT bit in the DcDMAConfiguration register must be set
to logic 0. The DMA Transfer Counter register must be programmed before any DMA
command is issued. The DMA transfer counter is set by writing from the LSByte to the
MSByte (address: 234h to 237h). The DMA transfer count is internally updated only after
the MSByte is written. Once the DMA transfer is started, the transfer counter starts
decrementing and on reaching 0, the DMA_XFER_OK bit is set and an interrupt is
generated by the ISP1761.
The DMA transfer starts once the DMA command is issued. Any of the following three
ways will terminate this DMA transfer:
There are two interrupts that are programmable to differentiate the method of DMA
termination: the INT_EOT and DMA_XFER_OK bits in the DMA Interrupt Reason register.
For details, see
Table 123. Control bits for GDMA read or write (opcode = 00h/01h)
Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the
other control signals are not 3-state.
The DMA Command register is a 1-byte register (for bit allocation, see
initiates all DMA transfer activities on the DMA controller. The register is write-only:
reading it will return FFh.
Remark: The DMA bus will be in 3-state until a DMA command is executed.
Control bits
Mode register
DMACLKON
DcDMAConfiguration register
MODE[1:0]
WIDTH
DIS_XFER_CNT Disables the use of the DMA Transfer Counter
DMA Hardware register
DACK_POL,
DREQ_POL
•
•
•
Detecting an internal EOT (short packet on an OUT token)
Resetting the DMA
GDMA stop command
W
6
1
1
Table
Description
Set DMACLKON to logic 1
Determines the active read or write data strobe signals
Selects the DMA bus width: 16 or 32 bits
Select the polarity of the DMA handshake signals
W
5
1
1
135.
Rev. 04 — 5 March 2007
DMA_CMD[7:0]
W
4
1
1
W
3
1
1
Hi-Speed USB OTG controller
W
2
1
1
W
1
1
1
Table
© NXP B.V. 2007. All rights reserved.
ISP1761
Reference
Table 101
Table 130
Table 132
124) that
116 of 163
W
0
1
1