ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 139

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
ISP1761_4
Product data sheet
15.1.2.2 Single cycle: DMA write
Table 171. DMA read (single cycle)
T
Table 172. DMA write (single cycle)
T
Symbol
t
t
t
Symbol
V
t
t
t
t
t
t
t
t
V
t
t
t
t
t
t
t
t
a34
a44
h14
a15
a25
h15
h25
su15
a35
cy15
w15
a15
a25
h15
h25
su15
a35
cy15
w15
amb
amb
Fig 25. DMA write (single cycle)
CC(I/O)
CC(I/O)
= 40 C to +85 C; unless otherwise specified.
= 40 C to +85 C; unless otherwise specified.
= 1.65 V to 1.95 V
= 3.3 V to 3.6 V
DREQ and DACK are active HIGH.
DREQ
WR_N
DACK
DATA
Parameter
DREQ de-assertion time after RD_N assertion
DACK de-assertion to next DREQ assertion time -
data hold time after RD_N de-asserts
Parameter
DACK assertion time after DREQ assertion
WR_N assertion time after DACK assertion
data hold time after WR_N de-assertion
DACK hold time after WR_N de-assertion
data set-up time before WR_N de-assertion
DREQ de-assertion time after WR_N assertion
last DACK strobe de-assertion to next DREQ
assertion time
WR_N pulse width
DACK assertion time after DREQ assertion
WR_N assertion time after DACK assertion
data hold time after WR_N de-assertion
DACK hold time after WR_N de-assertion
data set-up time before WR_N de-assertion
DREQ de-assertion time after WR_N assertion
last DACK strobe de-assertion to next DREQ
assertion time
WR_N pulse width
t
a25
Rev. 04 — 5 March 2007
t
a15
t
a35
t
w15
…continued
t
su15
data
t
h25
t
cy15
t
h15
Min
-
-
Hi-Speed USB OTG controller
Min
0
1
3
0
5.5
-
-
22
0
1
2
0
5.5
-
-
22
data 1
Max
18
56
5
Max
-
-
-
-
-
28
82
-
-
-
-
-
-
16
82
-
© NXP B.V. 2007. All rights reserved.
ISP1761
004aaa525
Unit
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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