ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 14

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
7. Functional description
ISP1761_4
Product data sheet
7.1 ISP1761 internal architecture: advanced NXP slave Host Controller
and hub
The EHCI block and the Hi-Speed USB hub block are the main components of the
advanced NXP slave Host Controller.
The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the
ISP1761 is adapted from
Universal Serial Bus Rev.
The internal Hi-Speed USB hub block replaces the companion Host Controller block used
in the original architecture of a Peripheral Component Interconnect (PCI) Hi-Speed USB
Host Controller to handle full-speed and low-speed modes. The hardware architecture in
the ISP1761 is simplified to help reduce cost and development time, by eliminating the
additional work involved in implementing the OHCI software required to support full-speed
and low-speed modes.
Figure 4
EHCI that has an internal port, the root hub port (not available externally), on which the
internal hub is connected. The three external ports are always routed to the internal hub.
The internal hub is a Hi-Speed USB hub including the TT.
Remark: The root hub must be enabled and the internal hub must be enumerated.
Enumerate the internal hub as if it is externally connected. For details, refer to
“Interfacing the ISP176x to the Intel PXA25x processor
At the Host Controller reset and initialization, the internal root hub port will be polled until a
new connection is detected, showing the connection of the internal hub.
The internal Hi-Speed USB hub is enumerated using a sequence similar to a standard
Hi-Speed USB hub enumeration sequence, and the polling on the root hub is stopped
because the internal Hi-Speed USB hub will never be disconnected. When enumerated,
the internal hub will report the three externally available ports.
shows the internal architecture of the ISP1761. The ISP1761 implements an
Rev. 04 — 5 March 2007
Ref. 2 “Enhanced Host Controller Interface Specification for
1.0”.
(AN10037)”.
Hi-Speed USB OTG controller
© NXP B.V. 2007. All rights reserved.
ISP1761
Ref. 5
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