ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 154

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ISP1761ET

Manufacturer Part Number
ISP1761ET
Description
USB Interface IC USB 2.0 HS OTG HOST
Manufacturer
NXP Semiconductors
Datasheet

Specifications of ISP1761ET

Operating Supply Voltage
1.65 V to 3.6 V
Lead Free Status / Rohs Status
 Details
Other names
ISP1761ET,557

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NXP Semiconductors
Table 181. Revision history
ISP1761_4
Product data sheet
Document ID
Modifications
(continued):
Release date
Table 52 “Power Down Control register (address 0354h) bit description”, Table 54 “HcInterrupt -
Host Controller Interrupt register (address 0310h) bit description” and Table 56 “HcInterruptEnable -
Host Controller Interrupt Enable register (address 0314h) bit description”: changed "reserved; write
logic 0" to "reserved; write reset value".
Table 54 “HcInterrupt - Host Controller Interrupt register (address 0310h) bit description”: updated
bit description of all bits.
Table 56 “HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit
description”: updated description of bit 6.
Section 8.5 “Philips Transfer Descriptor (PTD)”: updated the PTD description. Also, removed text
“(32 kB for high-speed)” from NrBytesToTransfer[14:0].
Table 64 “High-speed bulk IN and OUT: bit description” and Table 71 “Start and complete split for
bulk: bit description”: updated description of Mult[1:0], and access and description of X.
Table 66 “High-speed isochronous IN and OUT: bit description”: updated description of Mult[1:0].
Table 71 “Start and complete split for bulk: bit description”, Table 74 “Start and complete split for
isochronous: bit description” and Table 76 “Start and complete split for interrupt: bit description”:
updated description for HubAddress[6:0].
Section 10.1 “Introduction”: updated the third paragraph.
Section 10.1.1.5 “DMA stop and interrupt handling”: updated the first paragraph.
Added Section 10.3 “Clear buffer”.
Updated Section 10.4.2 “ISP1761 DMA”.
Updated Section 10.4.3 “ISP1761 peripheral suspend indication”.
Updated Table 96 “Endpoint access and programmability”.
Table 97 “Peripheral Controller-specific register overview” and Section 10.6.3 “Data Port register”:
changed the Data Port register size to 32 bits.
Section 10.5.1 “Address register”: changed the bus reset value of bit 7 from 1 to unchanged. Also
changed the second and third paragraphs.
Table 99 “Address register (address 0200h) bit description”: updated the bit description.
Section 10.5.3 “Interrupt Configuration register”: updated the first paragraph.
Table 106 “Debug register (address 0212h) bit allocation”: updated the bit description.
Section 10.5.5 “DcInterruptEnable register”: updated the fourth paragraph.
Section 10.6.1 “Endpoint Index register”: updated the remark and Table 110 “Endpoint Index
register (address 022Ch) bit description”.
Table 111 “Addressing of endpoint buffers”: updated.
Table 113 “Control Function register (address 0228h) bit description”: updated bits 4, 1 and 0
description.
Section 10.6.3 “Data Port register”: updated the remark.
Section 10.6.5 “DcBufferStatus register”: added remarks.
Section 10.6.6 “Endpoint MaxPacketSize register”: updated the second and last paragraphs.
Table 122 “Endpoint Type register (address 0208h) bit description”: updated description for bits 4
and 3.
Table 126 “DMA commands”: updated.
Section 10.7.2 “DMA Transfer Counter register”: removed the last paragraph.
Table 130 “DcDMAConfiguration - Device Controller Direct Memory Access Configuration register
(address 0238h) bit description”: updated.
Section 10.7.4 “DMA Hardware register”: reserved bit 5.
…continued
Data sheet status
Rev. 04 — 5 March 2007
Change notice
Hi-Speed USB OTG controller
Supersedes
© NXP B.V. 2007. All rights reserved.
ISP1761
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