ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 159

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
Table 100.Mode register (address 020Ch) bit allocation 105
Table 101.Mode register (address 020Ch) bit
Table 102.Interrupt Configuration register
Table 103.Interrupt Configuration register
Table 104.Debug mode settings . . . . . . . . . . . . . . . . . . .107
Table 105.Debug register (address 0212h) bit
Table 106.Debug register (address 0212h) bit
Table 107.DcInterruptEnable - Device Controller
Table 108.DcInterruptEnable - Device Controller
Table 109.Endpoint Index register (address 022Ch)
Table 110.Endpoint Index register (address 022Ch)
Table 111.Addressing of endpoint buffers . . . . . . . . . . .110
Table 112.Control Function register (address 0228h)
Table 113.Control Function register (address 0228h)
Table 114.Data Port register (address 0220h) bit
Table 115.Data Port register (address 0220h) bit
Table 116.Buffer Length register (address 021Ch) bit
Table 117.DcBufferStatus - Device Controller Buffer
Table 118.DcBufferStatus - Device Controller Buffer
Table 119.Endpoint MaxPacketSize register (address
Table 120.Endpoint MaxPacketSize register (address
Table 121.Endpoint Type register (address 0208h) bit
Table 122.Endpoint Type register (address 0208h) bit
Table 123.Control bits for GDMA read or write
Table 124.DMA Command register (address 0230h) bit
ISP1761_4
Product data sheet
description . . . . . . . . . . . . . . . . . . . . . . . . . . .105
(address 0210h) bit allocation . . . . . . . . . . . .106
(address 0210h) bit description . . . . . . . . . . .107
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Interrupt Enable register (address 0214h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Interrupt Enable register (address 0214h)
bit description . . . . . . . . . . . . . . . . . . . . . . . .109
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .110
bit description . . . . . . . . . . . . . . . . . . . . . . . .110
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .111
bit description . . . . . . . . . . . . . . . . . . . . . . . .111
description . . . . . . . . . . . . . . . . . . . . . . . . . . .112
description . . . . . . . . . . . . . . . . . . . . . . . . . . .112
description . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Status register (address 021Eh) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Status register (address 021Eh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .113
0204h) bit allocation . . . . . . . . . . . . . . . . . . . .114
0204h) bit description . . . . . . . . . . . . . . . . . .114
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
description . . . . . . . . . . . . . . . . . . . . . . . . . . .115
(opcode = 00h/01h) . . . . . . . . . . . . . . . . . . . .116
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Rev. 04 — 5 March 2007
Table 125.DMA Command register (address 0230h) bit
Table 126.DMA commands . . . . . . . . . . . . . . . . . . . . . . 117
Table 127.DMA Transfer Counter register
Table 128.DMA Transfer Counter register
Table 129.DcDMAConfiguration - Device Controller
Table 130.DcDMAConfiguration - Device Controller
Table 131.DMA Hardware register (address 023Ch)
Table 132.DMA Hardware register (address 023Ch)
Table 133.DMA Interrupt Reason register
Table 134.DMA Interrupt Reason register
Table 135.Internal EOT-functional relation with the
Table 136.DMA Interrupt Enable register (address
Table 137.DMA Endpoint register (address 0258h) bit
Table 138.DMA Endpoint register (address 0258h) bit
Table 139.DMA Burst Counter register (address 0264h)
Table 140.DMA Burst Counter register (address 0264h)
Table 141.DcInterrupt - Device Controller Interrupt
Table 142.DcInterrupt - Device Controller Interrupt
Table 143.DcChipID - Device Controller Chip
Table 144.Frame Number register (address 0274h) bit
Table 145.Frame Number register (address 0274h) bit
Table 146.DcScratch - Device Controller Scratch
Table 147.DcScratch - Device Controller Scratch
Table 148.Unlock Device register (address 027Ch) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
(address 0234h) bit allocation . . . . . . . . . . . . 118
(address 0234h) bit description . . . . . . . . . . . 118
Direct Memory Access Configuration
register (address 0238h) bit allocation . . . . . 118
Direct Memory Access Configuration
register (address 0238h) bit description . . . . 119
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 119
bit description . . . . . . . . . . . . . . . . . . . . . . . . 120
(address 0250h) bit allocation . . . . . . . . . . . . 120
(address 0250h) bit description . . . . . . . . . . . 120
DMA_XFER_OK bit . . . . . . . . . . . . . . . . . . . . 121
0254h) bit allocation . . . . . . . . . . . . . . . . . . . 121
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 122
bit description . . . . . . . . . . . . . . . . . . . . . . . . 123
register (address 0218h) bit allocation . . . . . 123
register (address 0218h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Identifier register (address 0270h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
register (address 0278h) bit allocation . . . . . 125
register (address 0278h) bit description . . . . 126
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Hi-Speed USB OTG controller
© NXP B.V. 2007. All rights reserved.
ISP1761
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