ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 23

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
ISP1761_4
Product data sheet
Additional IRQ characteristics can be adjusted in the Edge Interrupt Count register, as
necessary, applicable only when IRQ is set to be edge-active; a pulse of a defined width is
generated every time IRQ is active.
Bits 15 to 0 of the Edge Interrupt Count register define the IRQ pulse width. The maximum
pulse width that can be programmed is FFFFh, corresponding to a 1 ms pulse width. This
setting is necessary for certain processors that may require a different minimum IRQ
pulse width from the default value. The default IRQ pulse width set at power-on is
approximately 500 ns.
Bits 31 to 24 of the Edge Interrupt Count register define the minimum interval between two
interrupts to avoid frequent interrupts to the CPU. The default value of 00h attributed to
these bits determines the normal IRQ generation, without any delay. When a delay is
programmed and the IRQ becomes active after the respective delay, several IRQ events
may have already occurred.
All the interrupt events are represented by the respective bits allocated in the HcInterrupt
register. There is no mechanism to show the order or the moment occurrence of an
interrupt.
The asserted bits in the HcInterrupt register can be cleared by writing back the same
value to the HcInterrupt register. This means that writing logic 1 to each of the set bits will
reset that corresponding bits to the initial inactive state.
The IRQ generation rules that apply according to the preceding settings are:
The IRQ generation can also be conditioned by programming the IRQ Mask OR and IRQ
Mask AND registers.
3. Define the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW
4. Program the individual Interrupt Enable bits in the HcInterruptEnable register. The
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Mode Control register. These settings must match IRQ settings of the host processor.
By default, interrupt is level-triggered and active LOW.
software will need to clear the Interrupt Status bits in the HcInterrupt register before
enabling individual interrupt enable bits.
If an event of interrupt occurs but the respective bit in the Interrupt Enable register is
not set, then the respective HcInterrupt register bit is set but the interrupt signal is not
asserted.
An interrupt will be generated when interrupt is enabled and the respective bit in the
Interrupt Enable register is set.
For a level trigger, an interrupt signal remains asserted until the processor clears the
HcInterrupt register by writing logic 1 to clear the HcInterrupt register bits that are set.
If an interrupt is made edge-sensitive and is asserted, writing to clear the HcInterrupt
register will not have any effect because the interrupt will be asserted for a prescribed
amount of clock cycles.
The clock stopping mechanism does not affect the generation of an interrupt. This is
useful during the suspend and resume cycles, when an interrupt is generated to
signal a wake-up event.
Rev. 04 — 5 March 2007
Hi-Speed USB OTG controller
© NXP B.V. 2007. All rights reserved.
ISP1761
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