ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 30

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
ISP1761_4
Product data sheet
7.9 Power-On Reset (POR)
For an overcurrent limit of 500 mA per port, a PMOS transistor with R
approximately 100 m is required. If a PMOS transistor with a lower R
analog overcurrent detection can be adjusted using a series resistor; see
The digital overcurrent scheme requires using an external power switch with integrated
overcurrent detection, such as LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These
devices are controlled by PSWn_N signals corresponding to each port. In the case of
overcurrent occurrence, these devices will assert OCn_N signals. On OCn_N assertion,
the ISP1761 cuts off the port power by de-asserting PSWn_N. The external integrated
power switch will also automatically cut off the port power in the case of an overcurrent
event, by implementing a thermal shutdown. An internal delay filter will prevent false
overcurrent reporting because of in-rush currents when plugging a USB device. Because
of this internal delay, as soon as OCn_N is asserted, PSWn_N will switch off the external
PMOS in less than 15 ms.
Remark: If port 1 is used in OTG mode or as a dual-role device, the analog overcurrent
detection must be used, same on all three ports, because the same bit (bit 15 of the HW
Mode Control register) determines the overcurrent detection type.
When V
t
1.2 V.
To give a better view of the functionality,
dips at t2 to t3 and t4 to t5. If the dip at t4 to t5 is too short, that is, < 11 s, the internal
POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1,
the detector will see the passing of the trip level and a delay element will add another
t
PORP
PORP
Fig 10. Adjusting analog overcurrent detection limit (optional)
V
I
OC(nom)
PMOS
V
(1) R
PMOS
, will typically be 800 ns. The pulse is started when V
before it drops to 0.
CC(I/O)
= V
td
= 1 A
= voltage drop on PMOS
is optional.
OC(TRIP)
is directly connected to the RESET_N pin, the internal POR pulse width,
= V
Rev. 04 — 5 March 2007
5 V
TRIP(intrinsic)
REF5V
(I
Figure 11
OC(nom)
ISP1761
PSWn_N
shows a possible curve of V
R
td
), where:
004aaa662
Hi-Speed USB OTG controller
CC(5V0)
OCn_N
R
td
I
OC
(1)
rises above V
DSON
DSON
© NXP B.V. 2007. All rights reserved.
ISP1761
Figure
of
is used, the
CC(5V0)
TRIP
10.
30 of 163
of
with