ISP1761ET NXP Semiconductors, ISP1761ET Datasheet - Page 44

• Manufacturer Part Number: ISP1761ET
• Description: USB Interface IC USB 2.0 HS OTG HOST
• Manufacturer: NXP Semiconductors

Specifications of ISP1761ET

• Operating Supply Voltage: 1.65 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1761ET,557

NXP Semiconductors
[1]
ISP1761_4
Product data sheet
The reserved bits should always be written with the reset value.
Table 35.
Bit
31
30 to 16 -
15
14 to 12 -
11
10
9
8
7
6
5
4 to 3
2
1
0
Symbol
ALL_ATX_RESET
ANA_DIGI_OC
DEV_DMA
COMN_INT
COMN_DMA
DATA_BUS_WIDTH
-
DACK_POL
DREQ_POL
-
INTR_POL
INTR_LEVEL
GLOBAL_INTR_EN
HW Mode Control - Hardware Mode Control register (address 0300h) bit
description
Rev. 04 — 5 March 2007
Description
All ATX Reset: For debugging purposes (not used normally).
1 — Enable reset, then write back logic 0
0 — No reset
reserved; write logic 0
Analog Digital Overcurrent: This bit selects analog or digital
overcurrent detection on pins OC1_N/V
0 — Digital overcurrent
1 — Analog overcurrent
reserved; write logic 0
Device DMA: When this bit and bit 9 are set, DC_DREQ and
DC_DACK peripheral signals are selected on the HC_DREQ and
HC_DACK pins.
Common IRQ: When this bit is set, DC_IRQ will be generated on
the HC_IRQ pin.
Common DMA: When this bit and bit 11 are set, the DC_DREQ
and DC_DACK peripheral signals are routed to the HC_DREQ
and HC_DACK pins.
Data Bus Width:
0 — Defines a 16-bit data bus width
1 — Sets a 32-bit data bus width
Remark: Setting this bit will affect all the controllers on the chip:
Host Controller, Peripheral Controller and OTG Controller.
reserved; write logic 0
DACK Polarity:
1 — Indicates that the DACK input is active HIGH
0 — Indicates active LOW
DREQ Polarity:
1 — Indicates that the DREQ output is active HIGH
0 — Indicates active LOW
reserved; write logic 0
Interrupt Polarity:
0 — Active LOW
1 — Active HIGH
Interrupt Level:
0 — INT is level triggered.
1 — INT is edge triggered. A pulse of certain width is generated.
Global Interrupt Enable: This bit must be set to logic 1 to enable
IRQ signal assertion.
0 — IRQ assertion disabled. IRQ will never be asserted,
regardless of other settings or IRQ events.
1 — IRQ assertion enabled. IRQ will be asserted according to the
HcInterruptEnable register, and events setting and occurrence.
Hi-Speed USB OTG controller
BUS
, OC2_N and OC3_N.
© NXP B.V. 2007. All rights reserved.
ISP1761
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