SST25VF512-20-4C-SA Microchip Technology, SST25VF512-20-4C-SA Datasheet
SST25VF512-20-4C-SA
Specifications of SST25VF512-20-4C-SA
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SST25VF512-20-4C-SA Summary of contents
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... Erase or Program operation is less than alternative flash memory technologies. The SST25VF512 device operates with a single 2.7-3.6V power supply. The SST25VF512 device is offered in both 8-lead SOIC and 8-contact WSON packages. See Figure 1 for the pin assignments. The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc. ...
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... Data Sheet UNCTIONAL LOCK IAGRAM Address Buffers and Latches CE# ©2005 Silicon Storage Technology, Inc Decoder Control Logic Serial Interface SCK SI SO WP# HOLD# 2 512 Kbit SPI Serial Flash SST25VF512 SuperFlash Memory Y - Decoder I/O Buffers and Data Latches 1192 B1.5 S71192-08-000 11/05 ...
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... Kbit SPI Serial Flash SST25VF512 PIN DESCRIPTION CE Top View WP 1192 08-soic P1.4 8- SOIC LEAD FIGURE SSIGNMENTS TABLE ESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input ...
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... BFH Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). 48H The SST25VF512 supports both Mode 0 (0,0) and Mode 3 T2.5 1192 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 2, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... W OLD ONDITION Write Protection The SST25VF512 provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 4 for Block-Protection description ...
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... Memory Array) 1. Default at power-up for BP1 and BP0 is ‘11’. 2. Protection Level 1 (1/4 Memory Array) applies to Byte- Program, Sector-Erase, and Chip-Erase operations. It does not apply to Block-Erase operations. Default at Power- SST25VF512 R EGISTER 1 Protected Memory Area 0 None 1 0C000H-0FFFFH 0 08000H-0FFFFH 1 00000H-0FFFFH T4.5 1192 ...
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... Byte-Program mode. The default at power up is Byte-Program mode. Instructions Instructions are used to Read, Write (Erase and Program), and configure the SST25VF512. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, ...
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... CE# must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait T self-timed Byte-Program operation. See Figure 5 for the Byte-Program sequence ADD. ADD. MSB MSB HIGH IMPEDANCE 8 512 Kbit SPI Serial Flash SST25VF512 -A ]. CE# must N+1 N+2 N+3 N ...
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... Kbit SPI Serial Flash SST25VF512 Auto Address Increment (AAI) Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total program- ming time when the entire memory array pro- grammed ...
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... Block- BE Erase cycle. See Figure 8 for the Block-Erase sequence ADD. ADD. MSB MSB HIGH IMPEDANCE 10 512 Kbit SPI Serial Flash SST25VF512 ), remaining address bits can for the completion of the internal self ADD. 1192 F06.12 ]. Address bits [ Most 0 MS ...
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... Kbit SPI Serial Flash SST25VF512 Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain active low for the duration of the Chip-Erase instruction sequence ...
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... F35.6 EQUENCE CE# MODE MODE 0 SCK 04 SI MSB HIGH IMPEDANCE SO 1192 F36.6 EQUENCE Status-Register (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. 12 512 Kbit SPI Serial Flash SST25VF512 S71192-08-000 11/05 ...
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... Kbit SPI Serial Flash SST25VF512 Write-Status-Register (WRSR) The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register (EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The Write-Status-Register instruction must be executed immediately after the execution of the Enable- Write-Status-Register instruction (very next instruction bus cycle) ...
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... Data Sheet Read-ID The Read-ID instruction identifies the device as SST25VF512 and manufacturer as SST. The device infor- mation can be read from executing an 8-bit command, 90H or ABH, followed by address bits [A Read-ID instruction, the manufacturer’ located in CE# MODE MODE 0 SCK MSB HIGH IMPEDANCE SO Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE# ...
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... Kbit SPI Serial Flash SST25VF512 ELECTRICAL SPECIFICATIONS Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55° ...
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... BP 1. Relative to SCK. ©2005 Silicon Storage Technology, Inc. 512 Kbit SPI Serial Flash Minimum Specification Units 10,000 Cycles 100 Years 100 + 2.7-3.6V DD Min 100 SST25VF512 Test Method JEDEC Standard A117 JEDEC Standard A103 mA JEDEC Standard 78 T10.1 1192 Limits Max Units 20 MHz ...
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... Kbit SPI Serial Flash SST25VF512 CE# T CHH T CES SCK MSB SI SO HIGH-Z FIGURE 15 ERIAL NPUT IMING CE# T SCKH SCK T CLZ SO SI FIGURE 16 ERIAL UTPUT IMING ©2005 Silicon Storage Technology, Inc. T SCKF T SCKR D IAGRAM T SCKL T OH MSB IAGRAM 17 Data Sheet T CPH ...
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... Chip selection is not allowed. All commands are rejected by the device. V Min DD FIGURE 18 OWER UP IMING ©2005 Silicon Storage Technology, Inc HHH HLS T HLH PU-READ T PU-WRITE D IAGRAM 18 512 Kbit SPI Serial Flash SST25VF512 T HHS T LZ Device fully accessible Time 1192 F45.0 S71192-08-000 1192 F43.1 11/05 ...
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... Kbit SPI Serial Flash SST25VF512 V IHT INPUT V ILT AC test inputs are driven at V (0.9V IHT for inputs and outputs are V (0.7V HT FIGURE 19 NPUT UTPUT FIGURE 20 EST OAD XAMPLE ©2005 Silicon Storage Technology, Inc REFERENCE POINTS for a logic “1” and V (0 ...
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... XX Valid combinations for SST25VF512 SST25VF512-20-4C-SA SST25VF512-20-4C-QA SST25VF512-20-4C-SAE SST25VF512-20-4C-QAE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2005 Silicon Storage Technology, Inc. Suffix2 ...
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... Kbit SPI Serial Flash SST25VF512 PACKAGING DIAGRAMS Pin #1 Identifier TOP VIEW 5.0 4.8 4.00 3.80 6.20 5.80 Note: 1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0 Maximum allowable mold flash is 0. the package ends and 0.25 mm between leads. ...
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... Max 0.80 0. (WSON) UTLINE O LEAD 22 512 Kbit SPI Serial Flash SST25VF512 BOTTOM VIEW Pin #1 1.27 BSC 4.00 ± 0.10 0.48 0.35 3.40 ± 0.10 0.70 0.50 CROSS SECTION 0.80 0.70 8-wson-6x5-QA-8 1mm S71192-08-000 11/05 ...
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... Kbit SPI Serial Flash SST25VF512 TABLE 12 EVISION ISTORY Number 00 • Initial release 01 • Remove Cycles 6 & 7 for Read and Write operations. • Swapped Ready#/Busy logic busy not busy) • Change WP# description • Added SPI protocol timing diagram. • Updated all timing diagrams • ...