H5PS1G83EFR-S6C HYNIX SEMICONDUCTOR, H5PS1G83EFR-S6C Datasheet - Page 24

• Manufacturer Part Number: H5PS1G83EFR-S6C
• Description: 58T1895
• Manufacturer: HYNIX SEMICONDUCTOR

Specifications of H5PS1G83EFR-S6C

• Memory Type: SDRAM
• Memory Configuration: 128M X 8
• Access Time: 15ns
• Memory Case Style: FBGA
• No. Of Pins: 60
• Operating Temperature Range: 0°C To +85°C
• Memory Size: 1 Gbit
• Rohs Compliant: Yes

DQ output access time from CK/CK
DQS output access time from CK/CK
CK HIGH pulse width
CK LOW pulse width
CK half period
Clock cycle time, CL=x
DQ and DM input setup time
DQ and DM input hold time
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
First DQS latching transition to associated clock
edge
DQS input HIGH pulse width
DQS input LOW pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write preamble
Write postamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Activate to precharge command
Active to active command period for 1KB page size
products (x4, x8)
Active to active command period for 2KB page size
products (x16)
Four Active Window for 1KB page size products
Four Active Window for 2KB page size products
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge time
Rev. 0.4 / Nov 2008
Parameter
tAC
tDQSCK
tCH(avg)
tCL(avg)
tHP
tCK(avg)
tDS(base)
tDH(base)
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPRE
tWPST
tIS(base)
tIH(base)
tRPRE
tRPST
tRAS
tRRD
tRRD
tFAW
tFAW
tCCD
tWR
tDAL
Symbol
min(tCL(abs),
tHP - tQHS
WR+tnRP
tCH(abs))
2*tAC min
tAC min
- 0.25
min
3000
-450
-400
0.48
0.48
0.35
0.35
0.35
37.5
100
175
0.35
200
275
0.6
0.2
0.2
0.4
0.9
0.4
7.5
45
10
50
15
2
2
-
-
-
DDR2-667
tAC max
tAC max
tAC max
+ 0.25
70000
max
+450
+400
0.52
0.52
8000
240
340
0.6
1.1
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
min(tCL(abs),
tHP - tQHS
tCH(abs))
WR+tnRP
2*tAC min
tAC min
- 0.25
min
2500
-400
-350
0.48
0.48
0.35
0.35
125
0.35
0.35
175
250
0.6
0.2
0.2
0.4
0.9
0.4
7.5
50
45
10
35
45
15
2
2
-
-
-
DDR2-800
(DDR2-667 and DDR2-800)
tAC max
tAC max
tAC max
+ 0.25
70000
max
+400
+350
8000
0.52
0.52
200
300
0.6
1.1
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
H5PS1G43EFR
H5PS1G83EFR
H5PS1G63EFR
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Unit
nCK
nCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
6,7,8,20,28,31
6,7,8,21,28,31
5,7,9,22,29
5,7,9,23,29
Note
35,36
35,36
35,36
18,40
18,40
18,40
19,41
19,42
32
4,32
4,32
40
40
37
13
38
39
30
30
30
10
32
32
33
3
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