SPD6729QCE Intel, SPD6729QCE Datasheet
SPD6729QCE
Specifications of SPD6729QCE
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SPD6729QCE Summary of contents
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... PC applications typically access PC cards through the socket/card-services software interface. To assure full compatibility with existing socket/card-services software and PC-card applications, the register set in the PD6729 is a superset of the Intel 82365SL register set. The chip provides fully buffered PCMCIA interfaces, meaning that no external logic is required for buffering signals to/from the interface, and power consumption can be controlled by limiting signal transitions on the PCMCIA bus ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Contents 1.0 General Conventions 2.0 Pin Information 2.1 Pin Diagram.........................................................................................................13 2.2 Pin Description Conventions ...............................................................................13 2.3 Pin Descriptions ..................................................................................................15 3.0 Introduction to the PD6729 3.1 System Architecture ............................................................................................23 3.1.1 PCMCIA Basics......................................................................................23 3.1.2 PD6729 Windowing Capabilities ............................................................23 3.1.3 Zoomed Video Port ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 8.2 System I/O Map 0-1 Start Address Low.............................................................. 61 8.3 System I/O Map 0-1 Start Address High ............................................................. 62 8.4 System I/O Map 0-1 End Address Low ............................................................... 62 8.5 System I/O Map 0-1 ...
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PCMCIA Bus Timing ...........................................................................102 14.0 Package Dimensions 14.1 208-Pin MQFP Package Outline Drawing .........................................................108 14.2 208-Pin LQFP Package Outline Drawing ..........................................................109 15.0 Ordering Information Bit Index .......................................................................................................................................111 Figures 1 System Block Diagram .......................................................................................... Card Controller Form ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 11 ATA Pin Cross-Reference................................................................................... 91 12 General DC Specifications .................................................................................. 93 13 PCMCIA Bus Interface DC Specifications........................................................... 93 14 PCI Bus Interface DC Specifications................................................................... 94 15 Power Control Interface (+5V Powered) DC Specifications ................................ ...
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Revision History Revision Date 1.0 5/01 Datasheet PCI-to-PC Card (PCMCIA) Controller — PD6729 Description Initial release. 7 ...
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Product Features Single-chip PC Card controller Direct connection to PCI bus Direct connection of two PCMCIA sockets ZV Port support for multimedia applications Compliant with PCI 2.1 Compliant with PCMCIA 2.1 and JEIDA 4.1 82365SL-compatible register set, ExCA -compatible Automatic ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Embedded Systems Design Priorities • Minimum Power Consumption • High Performance • Hardware and Software Compatibility Figure 2. PC Card Controller Form Factor 10 Supporting Features Automatic Low-power Dynamic mode Suspend mode Mixed-voltage operation ...
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General Conventions The following general conventions apply to this document. Bits within words and words within various memory spaces are generally numbered with a 0 (zero) as the least-significant bit or word. For example, the least-significant bit of a ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 2.0 Pin Information The PD6729 device is packaged in a 208-pin MQFP (metric quad flat pack) or VQFP (very-tight- pitch quad flat pack) component package. The interface pins can be divided into four groups: ...
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Pin Diagram Figure 3. PD6729 Pin Diagram B_A11 157 B_-IORD 158 B_SOCKET_VCC B_A9 159 B_-IOWR 160 B_SOCKET_VCC 161 B_A8 162 B_A17 163 B_A13 164 B_A18 165 B_A14 166 B_A19 167 B_-WE 168 B_A20 169 B_RDY/-IREQ 170 B_A21 171 B_A16 ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller • An asterisk (*) at the end of a pin name indicates an active-low signal that is a general- interface for the PD6729. • Pins marked with a dagger (†) in the pin description ...
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Power Type +5V: powered from a 5-volt power supply (in 1 most systems, see description of +5V pin in Table A_SOCKET_VCC: powered from the Socket and 51 of Socket A B_SOCKET_VCC: powered from the Socket 3 B ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Table 1. PCI Bus Interface Pins (Sheet Pin Name Target Ready: This output indicates the PD6729’s ability to complete the current data phase of the TRDY# transaction. TRDY# is used in ...
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Table 1. PCI Bus Interface Pins (Sheet Pin Name Interrupt Request: These outputs indicate programmable interrupt requests generated from any of a number of card actions. Although there is no IRQ[12:9] specific mapping requirement for connecting interrupt ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Table 2. Socket Interface Pins (Sheet Pin Name Description Register Access: In Memory Card Interface mode, this output chooses between attribute and common memory. In -REG I/O Card Interface mode, ...
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Table 2. Socket Interface Pins (Sheet Pin Name Description Ready / Interrupt Request: In Memory Card Interface mode, this input indicates to RDY/-IREQ † the PD6729 that the card is either ready or busy. In I/O ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Table 2. Socket Interface Pins (Sheet Pin Name Description Voltage Sense 2: This pin is used in conjunction with VS1 to determine the operating voltage of the card. This pin ...
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Table 3. Power Control and General Interface Pins (Sheet Pin Name Description This active-low output controls the 5-volt supply to the socket’s V -VCC_5 active-low level of this output is mutually exclusive with that of -VCC_3. Speaker ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Table 5. Pin Usage Summary Pin Group PCI bus interface pins Socket interface pins Power control and general interface pins Power, ground, and no-connect pins 22 Pin Quantity 63 122 10 13 Total: 208 ...
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Introduction to the PD6729 3.1 System Architecture This section describes PCMCIA basics, windowing, socket power management features, interrupts, device power management, write FIFO usage, bus sizing, programmable PCMCIA timing, and ATA mode operation. 3.1.1 PCMCIA Basics PCMCIA is an ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Having five memory windows per socket allows a memory-type card to be accessed through four memory windows programmed for common memory access, (allowing PC-type expanded- memory-style management), leaving the fifth memory window available to ...
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Caution: The windows of the PD6729 should never be allowed to overlap with each other or the other devices in the system. This would cause signal collisions, resulting in erratic behavior. Figure 4. Memory Window Organization PCI Memory Address Space ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Figure 5. I/O Window Organization PCI I/O Address Space 4 Gbytes System I/O Map End Address Registers I/O Window System I/O Map Start Address Registers 3.1.3 Zoomed Video Port The PD6729 supports the implementation ...
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Figure 6. A Typical ZV Port Implementation TV DRAM ANALOG ENCODER GD7XXX PD6729 MOTHERBOARD 3.1.4 Interrupts In a PC-compatible system with a PCI bus, there usually are two types of interrupts in use: • Four PCI-defined, active-low, open-drain, shared interrupt ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Figure 7. A Common Mapping of PD6729 Interrupt Pins to System Interrupt Signals 3.1.4.1 Classes of Interrupts The PD6729 supports two classes of interrupts: • Socket or card interrupts initiated by a PCMCIA I/O-type ...
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PCMCIA cards with differing I/O functionalities to be connected to appropriate non-conflicting IRQ locations, the PD6729 can steer the interrupt signal from a PCMCIA card to any one of the ten different hardware interrupt lines. For some I/O-type cards, software ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller The PD6729 power can be further managed by controlling socket power as outlined in Power Management Features” on page or automatically when cards are inserted or removed. The PD6729 provides six pins per socket ...
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Write FIFO To increase performance when writing to PCMCIA cards, two, independent, four-word-deep write FIFOs are used. Writes to PCMCIA cards will complete without holding off the PCI bus until the FIFO is full. Note: Register states should only ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Figure 8. Indexed 8-Bit Register Structure X Figure 9. Indexed 8-Bit Register Example The following code segment demonstrates use of an indexed 8-bit register: mov dx, XXX mov al, 02h mov ah, 3Ch out ...
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Extension Control 1 register example ;Code section mov dx, Base_IO_Address mov al, Extended_Index mov ah, Ext_Cntrl_1 out dx, ax mov al, Index_Reg out dx, al inc dx in al, dx 3.3 Power-On Setup Following RST#-activated ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 4.0 Register Description Conventions Register Headings The description of each register starts with a header containing the following information: Header Field Register Name This indicates the register name. This is added to the base ...
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Keyword Description Indicates that the function described in the Enable rest of the bit name is active when the bit is a ‘1’. Indicates that the function described in the Disable rest of the bit name is active when the ...
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... Bits 31-16: Device ID This read-only field is the device identification. This field always reads back 1100h for the PD6729. Revision number identification for the PD6729 part itself is indicated by the Mask Revision byte at extended index 39h. 1. Now supported by Intel Corp. 36 Bit 29 Bit 28 Bit 27 ...
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Command and Status Configuration Register Name: Command and Status Offset: 04h Bit Bit 31 30 Address/ System 3 Data Parity Error Status Error (SERR#) (high) Detected Generated RW:0 RW:0 Bit Bit Status (low) Bit Bit 15 ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bit 6: Parity Error Check/Report Enable This bit enables all parity-reporting-related circuitry, except for bit 31 of this register. 0 Parity checking and reporting in the PD6729 disabled. 1 Parity checking and reporting in ...
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No data parity errors detected. 1 Address or data parity error detected. 5.3 Revision ID and Class Code Configuration Register Name: Revision ID and Class Code Offset: 08h Bit Bit Class Code (high) Bit Bit 23 ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 5.4 Cache Line Size, Latency Timer, Header Type, and BIST Configuration Register Name: Cache Line Size, Latency Timer, Header Type, and BIST Offset: 0Ch Bit 31 Bit 30 3 BIST Bit 23 Bit 22 ...
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Base Address 0 Configuration Register Name: Base Address 0 Offset: 10h Bit 31 Bit 30 Byte3 Bit 23 Bit 22 Byte 2 Bit 15 Bit 14 Byte1 Bit 7 Bit 6 Byte 0 This is the PCI I/O address ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 5.6 Interrupt Line, Interrupt Pin, Min_Gnt, and Max_Lat Configuration Register Name: Interrupt Line, Interrupt Pin, Min_Gnt, and Max_Lat Offset: 3Ch Bit 31 Bit 30 Byte 3 Max_Lat Bit 23 Bit 22 Byte 2 Min_Gnt ...
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Operation Registers The PD6729’s internal Device Control, Window Mapping, Extension, and Timing registers are accessed through a pair of Operation registers — an Index register and a Data register. The Index register is accessed at the address programmed in ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Figure 11. Socket/Register Index Space When viewed as a 7-bit value, the contents of this register completely specify a single internal- register byte. For example, when the value of this register is in the ...
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Table 7. Index Registers (Sheet Register Name System Memory Map 0 Start Address Low System Memory Map 0 Start Address High System Memory Map 0 End Address Low System Memory Map 0 End Address High Card Memory ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Table 7. Index Registers (Sheet Register Name Extended Index: Scratchpad Reserved Reserved Extension Control 1 Reserved System Memory Map 0 Upper Address System Memory Map 1 Upper Address System Memory Map ...
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Table 7. Index Registers (Sheet Register Name Setup Timing 0 Command Timing 0 Recovery Timing 0 Setup Timing 1 Command Timing 1 Recovery Timing 1 Reserved NOTES: 1. This register affects both sockets (it is not specific ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 7.0 Device Control Registers 7.1 Chip Revision Register Name: Chip Revision Index: 00h Bit 7 Bit 6 Bit 5 Reserved Interface ID R:10 R:0 NOTE: 1. Value for the current stepping only. Bits 3-0: ...
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Interface Status Register Name: Interface Status Index: 01h Bit Bit Bit 7 6 RDY Card Power 1 Ready/Busy R:1 R:0 R NOTES: 1. Bit 7 always reads a ‘1’ on the PD6729. 2. Bit 5 indicates the ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bit 4: Write Protect 0 Card is not write protected. 1 Card is write protected. In Memory Card Interface mode, this bit indicates the state of the WP/-IOIS16 pin card. This bit is not ...
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Table 8. Enabling of Socket Power Controls Both -CD1 RST# Level and -CD2 are Active (Low) V Power CC (Bit 4) Low X X High X High X High No High Yes Table 9. Enabling of Output Signals to Socket ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bit 4: V Power CC Power is not applied to the card: the -VCC_3 and -VCC_5 socket power control pins are 0 inactive (high). Power is applied to the card: if bit 5 is ...
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Bits 3-0: IRQ Level 0000 IRQ disabled 0001 Reserved 0010 Reserved 0011 IRQ3 (INTA#) 0100 IRQ4 (INTB#) 0101 IRQ5 (INTC#) 0110 Reserved 0111 IRQ7 (INTD#) 1000 Reserved 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 Reserved 1110 IRQ14 (This ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bit 6: Card Reset* 0 The RESET signal to the card socket is set active (high for normal, low for ATA mode). 1 The RESET signal to the card socket is set inactive (low ...
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In Memory Card Interface mode, this bit is set to a ‘1’ when the BVD1/-STSCHG/-RI pin (see Table 2) changes from high to low, indicating a battery dead condition. In I/O Card Interface mode, this bit is set to a ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller This register controls which status changes cause management interrupts as well as at which pin the management interrupts will appear. Bit 0: Battery Dead Or Status Change Enable 0 Battery Dead Or Status Change ...
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Bits 7-4: Management IRQ 0000 IRQ disabled 0001 Reserved 0010 Reserved 0011 IRQ3 (INTA#) 0100 IRQ4 (INTB#) 0101 IRQ5 (INTC#) 0110 Reserved 0111 IRQ7 (INTD#) 1000 Reserved 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101 Reserved 1110 IRQ14 (This ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bit 1: Memory Map 1 Enable 0 Memory Window Mapping registers for Memory Window 1 disabled. 1 Memory Window Mapping registers for Memory Window 1 enabled. When this bit is a ‘1’, the Memory ...
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Bit 7: I/O Map 1 Enable 0 I/O Window Mapping registers for I/O Window 1 disabled. 1 I/O Window Mapping registers for I/O Window 1 enabled. When this bit is a ‘1’, the I/O Window Mapping registers for I/O Window ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 8.0 I/O Window Mapping Registers Caution: Be sure that the I/O windows do not map to the Base Address 0 register programmed at offset 10h. 8.1 I/O Window Control Register Name: I/O Window Control ...
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Bit 4: I/O Window 1 Size 0 8-bit data path to I/O Window 1. 1 16-bit data path to I/O Window 1. When bit 5 of this register is a ‘0’, this bit determines the width of the data path ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bits 7-0: Start Address 7-0 This register contains the least-significant byte of the address that specifies where in the I/O space the corresponding I/O map will begin. I/O accesses that are equal or above ...
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Bits 7-0: End Address 7-0 This register contains the least-significant byte of the address that specifies where in the I/O space the corresponding I/O map will end. I/O accesses that are equal or below this address and equal or above ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Index (Socket A)Card I/O Map Offset Address Low 36h Card I/O Map 0 Offset Address Low 38h Card I/O Map 1 Offset Address Low Bits 7-1: Offset Address 7-1 This register contains the least-significant ...
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Memory Window Mapping Registers The following information about the memory map windows is important: • The memory window mapping registers determine where in the PCI memory space and PC card memory space accesses will occur. There are five memory ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bits 7-0: Start Address 19-12 This register contains the least-significant byte of the address that specifies where in the memory space the corresponding memory map will begin. Memory accesses that are equal or above ...
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System Memory Map 0-4 End Address Low Register Name: System Memory Map 0-4 End Address Low Index: 12h, 1Ah, 22h, 2Ah, 32h Bit 7 Bit 6 Bit 6 There are five separate System Memory Map End Address Low registers, ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 23h System Memory Map 2 End Address High 2Bh System Memory Map 3 End Address High 33h System Memory Map 4 End Address High Bits 3-0: End Address 23-20 This field contains the most-significant ...
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The most-significant six bits are located in the Card Memory Map 0-4 Offset Address High register. 9.6 Card Memory Map 0-4 Offset Address High Register Name: Card Memory Map 0-4 Offset Address High Index: 15h, 1Dh, 25h, 2Dh, 35h Bit ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 10.0 Extension Registers 10.1 Misc Control 1 Register Name: Misc Control 1 Index: 16h Bit 7 Bit 6 Bit 5 Inpack Scratchpad Bits Enable RW:0 RW:00 Bit 0: Multimedia Enable 0 Socket address lines ...
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Figure 12. Pulse Mode Interrupts HI-Z IRQ[XX] HI-Z = high impedance Bit 3: Pulse System IRQ 0 Interrupts are passed to the IRQ[XX] pin as level-sensitive. When an interrupt occurs, the IRQ[XX] pin is driven with the pulse train shown ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bit 7: FIFO Status / Flush FIFO Value 0 FIFO not empty 1 FIFO empty This bit controls FIFO operation and reports FIFO status. When this bit is set to a ‘1’ during write ...
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Bit 1: Low-Power Dynamic Mode 0 Clock runs always. 1 Normal operation, stop clock when possible. This bit determines whether Low-power Dynamic mode is enabled. Leaving this bit set to ‘1’ allows automatic reduction in power consumption during periods of ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 10.4 Chip Information Register Name: Chip Information Index: 1Fh Bit 7 Bit 6 Bit 5 PD6729 PC Card Controller Identification R:11 NOTE: 1. This read-only value depends on the revision level of the PD6729 ...
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This bit reconfigures the particular socket as an ATA drive interface. Refer to for PCMCIA socket pin definitions in ATA mode. Bit 1: Speaker Is LED Input 0 Normal operation. The PCMCIA -SPKR pin will be used to drive LED_OUT* ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 10.6 Extended Index Register Name: Extended Index Index: 2Eh Bit Bit Bit 7 6 This register controls which of the following registers at index 2Fh can be accessed: Register Name at Index 2Fh Scratchpad ...
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Extended Data Register Name: Extended Data Index: 2Fh Bit Bit Bit 7 6 The data in this register allows the registers indicated by the Extended Index register to be read and written. The value of this register is the ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller This bit allows the LED_OUT* pin to reflect any activity in the card. Whenever PCMCIA cycles are in process to or from a card in either socket, LED_OUT* will be active low. Bit 3: ...
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These bits are used in comparing PCI Address bits 31-24 for each memory window (0-4). These bits are used in conjunction with the System Memory Map 0-4 Start Address and System Memory Map 0-4 End Address registers. 10.7.3 Misc Control ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 10.8.1 Mask Revision Byte Register Name: Mask Revision Byte Index: 2Fh Bit Bit Bit 7 6 Bits 7:0 — Mask Revision These bits indicate the mask revision of the device. 10.8.2 Product ID Byte ...
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Capability Byte A Register Name: Device Capability Byte A Index: 2Fh Bit Bit Bit 23 22 GPSTB Per Skt LED RFU Capable R:0 R:0 R:1 Bit 23: Per-Socket LED A ‘0’ indicates that the PD6729 uses a single ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 10.8.4 Device Capability Byte B Register Name: Device Capability Byte B Index: 2Fh Bit Bit Bit 31 30 Extended RFU (ZV) RFU (ZV) Def’s R:0 R:0 R:0 Bit 31: Extended Definitions A value of ...
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Bit 39: RI_OUT Wired A ‘1’ indicates that in the system implementation, a pin on the device designated as ‘RI_OUT’ has been connected to ring indicate circuitry. Socket services must set register 1E bit ‘1’, thereby enabling ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bit 43: X.V capable A value of ‘1’ indicates that X.X V voltage source is available for the powering of PC cards in this system. A value of ‘0’ indicates that X.X V voltage ...
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Bit 50 — SPKR Wired A value of ‘1’ indicates that in the particular system implementation a speaker is connected to the SPKR_OUT pin. A value of ‘0’ indicates that a speaker is not connected to the SPKR_OUT pin. Bit ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bit 56 — CLKRUN Wired A value of ‘1’ indicates that the system implementation wires a CLKRUN signal to a device’s CLKRUN pin. supports CLKRUN protocol. Since the PD6729 does not have a CLKRUN ...
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Timing Registers The following information about the timing registers is important: • All timing registers take effect immediately and should only be changed when the FIFO is empty (see “FIFO Control” on page • Selection of Timer Set 0 ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bits 7-6: Setup Prescalar Select 00 N pres = pres = pres = 256 11 N pres = 4096 This field chooses one of four prescalar values N ...
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Bits 5-0: Command Multiplier Value This field indicates an integer value N 7-6) to control the length that a command is active. Bits 7-6: Command Prescalar Select 00 N pres = pres = ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Bits 5-0: Recovery Multiplier Value This field indicates an integer value N 7-6) to control the length of recovery time after a command is active. Bits 7-6: Recovery Prescalar Select 00 N pres = ...
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ATA Mode Operation The PD6729 card interfaces can be dynamically configured to support a PCMCIA-compatible ATA disk interface (commonly known as ‘IDE’) instead of the standard PCMCIA card interface. Disk drives that can be made mechanically-compatible with PCMCIA card ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Table 11. ATA Pin Cross-Reference (Sheet PCMCIA PCMCIA Card Socket Pin Interface Number Function ...
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Electrical Specifications 13.1 Absolute Maximum Ratings Ambient temperature under bias 0Storage temperature Voltage on any pin (with respect to ground) Operating power dissipation Power dissipation during Suspend mode Power supply voltage Injection current (latch up) NOTE: 1. Stresses above ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Table 13. PCMCIA Bus Interface DC Specifications (Sheet Symbol Parameter V Input low voltage IL V Input high voltage CMOS IHC V Input low voltage CMOS ILC V Output high voltage ...
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Table 15. Power Control Interface (+5V Powered) DC Specifications Symbol Parameter +5V +5V supply voltage V Input high voltage IH V Input low voltage IL V Output high voltage OH V Output high voltage CMOS OHC V Output low voltage ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 13.3 AC Timing Specifications This section includes system timing requirements for the PD6729. Unless otherwise specified, timings are provided in nanoseconds (ns), at TTL input levels, with the ambient temperature varying from 0 C ...
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Table 19. FRAME#, AD[31:0], C/BE[3:0]#, and DEVSEL# (Sheet Symbol Parameter t C/BE[3:0]# (byte enable) setup to PCI_CLK 8 t DEVSEL# delay from PCI_CLK 9 t DEVSEL# high before HI-Z 10 Figure 13. FRAME#, AD[31:0], C/BE[3:0]#, and DEVSEL# ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Table 20. TRDY# and STOP# Delay Symbol Parameter t TRDY# active delay from PCI_CLK 1 t TRDY# inactive delay from PCI_CLK 2 t TRDY# high before HI STOP# active delay from PCI_CLK ...
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Figure 14. IDSEL Timing in a Configuration Cycle (PCI PCI_CLK IDSEL FRAME# HI-Z AD[7:0] HI-Z C/BE[3:0]# HI-Z = high impedance Table 23. PAR Timing Symbol t PAR setup to PCI_CLK (input to PD6729 PAR hold from PCI_CLK (input ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Figure 15. PAR Timing (PCI PCI_CLK FRAME# HI-Z AD[31:0] Address HI-Z C/BE[3:0]# Command HI-Z PAR HI-Z = high impedance PAR goes high or low depending on AD[31:0] and C/BE[3:0]# values. † 13.3.2 System Interrupt ...
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PCMCIA Bus Timing Calculations Calculations for minimum PCMCIA cycle Setup, Command, and Recovery timings are made by first calculating factors derived from the applicable timer set’s timing registers and then by applying the factor to an equation relating it ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller 13.3.4 PCMCIA Bus Timing Table 25. Memory Read/Write Timing Symbol -REG, -CE[2:1], Address, and Write Data setup to Command active 2 t Command pulse width 2 t Address hold and Write ...
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Table 26. Word I/O Read/Write Timing Symbol t -REG or Address setup to Command active Command pulse width 2 t Address hold and Write Data valid from Command inactive 3 t -WAIT active from Command active 4 ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Figure 18. Word I/O Read/Write Timing -REG, A[25: -IOWR, -IORD -WAIT t ref -IOIS16 -CE1 -CE2 D[15:0] Write Cycle D[15:0] Read Cycle Table 27. PCMCIA Read/Write Timing when System is 8-Bit Symbol ...
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Figure 19. PCMCIA Read/Write Timing when System is 8 Bit (SBHE Tied High) -REG, A[25: -IOWR, -IORD, -OE, -WE -CE1 D[7:0] Write Cycle D[7:0] Read Cycle D[15:8] Read or Write Cycle Table 28. Normal Byte Read/Write Timing Symbol ...
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PD6729 — PCI-to-PC Card (PCMCIA) Controller Figure 20. Normal Byte Read/Write Timing (that is, all other byte accesses, including odd I/O cycles where -IOIS16 is low) -REG, A[25: -IOWR, -IORD, -OE, -WE -CE1 -CE2 D[7:0] Write Cycle D[7:0] ...
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Figure 21. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing -REG, A[25: -IOIS16 -CE2 -CE1 t 4 -IOWR, -IORD D[7:0] Write Cycle D[7:0] Read Cycle D[15:8] Read or Write Cycle Datasheet PCI-to-PC Card (PCMCIA) Controller — PD6729 ...
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... Before beginning any new design with this device, please contact for the latest package information. 108 30.35 (1.195) 30.85 (1.215) 27.90 (1.098) 28.10 (1.106) 0.13 (0.005) 0.28 (0.011) SPD6729QCE 208-Pin MQFP Pin 1 Indicator 25.50 (1.004) REF 3.17 (0.125) 0.40 (0.016) 3.67 (0.144) 0.75 (0.030) 27 ...
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... NOTES: 1. Dimensions are in millimeters (inches), and controlling dimension is millimeter. 2. Drawing above does not reflect exact package pin count. 3. Before beginning any new design with this device, please contact Intel for the latest package information. Datasheet PCI-to-PC Card (PCMCIA) Controller — PD6729 29 ...
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... PD6729 — PCI-to-PC Card (PCMCIA) Controller 15.0 Ordering Information The order number for the part is: 110 SPD6729QCE Product line: Portable Devices Part number DZPD6729VCE Product line: Portable Devices Part number Revision Temperature range Commercial Package type: MQFP Metric quad flat pack ...
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Bit Index Symbols +5V 21 Numerics 5V Core bit 73 A A[25:0] 18 A_pin name 18 A21 bit 75 A22 bit 75 A23/VU bit 75 A24/M/S* bit 75 A25/CSEL bit 75 AC specifications 96–107 AD[31:0] 15 Address/Data Parity Error Detected ...
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CORE_GND 21 CORE_VDD 21 D D[15:0] 18 Data register 47 DC specifications 93–95 Device Control registers 48–59 Device ID bits 36 DEVSEL# 16 DEVSEL# Timing bits 38 E End Address 15-8 bits 63 End Address 19-12 bits 67 End Address ...
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L -LED 19 LED Activity Enable bit 77, 79 LED_OUT* 21 Low-Power Dynamic Mode bit 73 Low-power Dynamic mode, description 29 M Manage Int Enable bit 53 Management Interrupt Configuration register 55 Management IRQ bits 57 Mapping Enable register 57 ...
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Setup Multiplier Value bits 87 Setup Prescalar Select bits 88 Setup Timing 0-1 registers 87 socket accessing specific registers 44 interface pins 18–20 register per 34 Socket A/B VS1/VS2 Input bits 86 Socket Index bit 43 SOCKET_VCC 20 Speaker Enable ...
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W -WAIT 19 Wait Cycle Enable bit 38 waveform. See timing -WE 18 Window Data Size bit 66 windowing 23 Datasheet WP/-IOIS16 18 write FIFO 31 Write Protect bit 50 Zoomed Video Port 26 115 ...
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