XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 10

• Manufacturer Part Number: XCB56362PV100
• Description: DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
• Manufacturer: Freescale Semiconductor

Specifications of XCB56362PV100

• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 33 KB
• Device Million Instructions Per Second: 100 MIPS

Ground
2.3
2.4
2-4
Signal Name
CLKOUT
Ground Name
EXTAL
GND
GND
GND
GND
GND
GND
GND
GND
Q
D
C
S
A (4)
Ground
Clock and PLL
P1
P
H
(2)
(4)
(4)
(2)
Output
Type
Input
PLL Ground—GND
extremely low-impedance path to ground. V
located as close as possible to the chip package. There is one GND
PLL Ground 1—GND
extremely low-impedance path to ground. There is one GND
Quiet Ground—GND
tied externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There are four GND
Address Bus Ground—GND
connection must be tied externally to all other chip ground connections. The user must provide adequate
external decoupling capacitors. There are four GND
Data Bus Ground—GND
must be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are four GND
Bus Control Ground—GND
be tied externally to all other chip ground connections. The user must provide adequate external
decoupling capacitors. There are two GND
Host Ground—GND
externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors. There is one GND
SHI, ESAI, DAX, and Timer Ground—GND
I/O drivers. This connection must be tied externally to all other chip ground connections. The user must
provide adequate external decoupling capacitors. There are two GND
State during Reset
Chip-Driven
Input
P
Table 2-4 Clock and PLL Signals
H
Q
is a ground dedicated for PLL use. The connection should be provided with an
P1
is an isolated ground for the HDI08 I/O drivers. This connection must be tied
DSP56362 Technical Data, Rev. 4
is an isolated ground for the internal processing logic. This connection must be
is a ground dedicated for PLL use. The connection should be provided with an
External Clock Input—An external clock source must be connected to EXTAL
in order to supply the clock to the internal clock generator and PLL.
This input cannot tolerate 5V.
Clock Output—CLKOUT provides an output clock synchronized to the internal
core clock phase.
If the PLL is enabled and both the multiplication and division factors equal one,
then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of EXTAL.
CLKOUT is not functional at frequencies of 100 MHz and above.
D
is an isolated ground for sections of the data bus I/O drivers. This connection
C
Table 2-3 Grounds
H
A
is an isolated ground for the bus control I/O drivers. This connection must
Q
is an isolated ground for sections of the address bus I/O drivers. This
connection.
connections.
C
D
CCP
S
connections.
connections.
Description
is an isolated ground for the SHI, ESAI, DAX, and Timer
should be bypassed to GND
A
connections.
Signal Description
P1
connection.
P
S
connection.
connections.
P
by a 0.47 µF capacitor
Freescale Semiconductor