XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 14

• Manufacturer Part Number: XCB56362PV100
• Description: DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
• Manufacturer: Freescale Semiconductor

Specifications of XCB56362PV100

• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 33 KB
• Device Million Instructions Per Second: 100 MIPS

Interrupt and Mode Control
2.6
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
2-8
Signal Name
MODB/IRQB
MODC/IRQC
MODA/IRQA
Interrupt and Mode Control
Type
Input
Input
Input
State during Reset
Input
Input
Input
Table 2-8 Interrupt and Mode Control
DSP56362 Technical Data, Rev. 4
Mode Select A/External Interrupt Request A—MODA/IRQA is an
active-low Schmitt-trigger input, internally synchronized to the DSP clock.
MODA/IRQA selects the initial chip operating mode during hardware reset
and becomes a level-sensitive or negative-edge-triggered, maskable
interrupt request input during normal instruction processing. MODA,
MODB, MODC, and MODD select one of 16 initial chip operating modes,
latched into the OMR when the RESET signal is deasserted. If IRQA is
asserted synchronous to CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and asserting IRQA to exit the
wait state. If the processor is in the stop standby state and the
MODA/IRQA pin is pulled to GND, the processor will exit the stop state.
This input is 5 V tolerant.
Mode Select B/External Interrupt Request B—MODB/IRQB is an
active-low Schmitt-trigger input, internally synchronized to the DSP clock.
MODB/IRQB selects the initial chip operating mode during hardware reset
and becomes a level-sensitive or negative-edge-triggered, maskable
interrupt request input during normal instruction processing. MODA,
MODB, MODC, and MODD select one of 16 initial chip operating modes,
latched into OMR when the RESET signal is deasserted. If IRQB is
asserted synchronous to CLKOUT, multiple processors can be
re-synchronized using the WAIT instruction and asserting IRQB to exit the
wait state.
This input is 5 V tolerant.
Mode Select C/External Interrupt Request C—MODC/IRQC is an
active-low Schmitt-trigger input, internally synchronized to the DSP clock.
MODC/IRQC selects the initial chip operating mode during hardware reset
and becomes a level-sensitive or negative-edge-triggered, maskable
interrupt request input during normal instruction processing. MODA,
MODB, MODC, and MODD select one of 16 initial chip operating modes,
latched into OMR when the RESET signal is deasserted. If IRQC is
asserted synchronous to CLKOUT, multiple processors can be
resynchronized using the WAIT instruction and asserting IRQC to exit the
wait state.
This input is 5 V tolerant.
Signal Description
Freescale Semiconductor