XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 22

• Manufacturer Part Number: XCB56362PV100
• Description: DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
• Manufacturer: Freescale Semiconductor

Specifications of XCB56362PV100

• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 33 KB
• Device Million Instructions Per Second: 100 MIPS

Enhanced Serial Audio Interface
2.9
2-16
Signal
Name
HCKR
HCKT
PC2
PC5
FSR
PC1
Enhanced Serial Audio Interface
Input, Output, or
Input, Output, or
Input, Output, or
Input or Output
Input or Output
Input or Output
Disconnected
Disconnected
Disconnected
Signal Type
Table 2-11 Enhanced Serial Audio Interface Signals
State during Reset
GPIO Disconnected High Frequency Clock for Receiver—When programmed as an
GPIO Disconnected High Frequency Clock for Transmitter—When programmed as an
GPIO Disconnected Frame Sync for Receiver—This is the receiver frame sync
DSP56362 Technical Data, Rev. 4
input, this signal provides a high frequency clock source for the ESAI
receiver as an alternate to the DSP core clock. When programmed as
an output, this signal can serve as a high-frequency sample clock
(e.g., for external digital to analog converters [DACs]) or as an
additional system clock.
Port C 2—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
input, this signal provides a high frequency clock source for the ESAI
transmitter as an alternate to the DSP core clock. When programmed
as an output, this signal can serve as a high frequency sample clock
(e.g., for external DACs) or as an additional system clock.
Port C 5—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
input/output signal. In the asynchronous mode (SYN=0), the FSR pin
operates as the frame sync input or output used by all the enabled
receivers. In the synchronous mode (SYN=1), it operates as either the
serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable
control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is
determined by the RFSD bit in the RCCR register. When configured
as the output flag OF1, this pin will reflect the value of the OF1 bit in
the SAICR register, and the data in the OF1 bit will show up at the pin
synchronized to the frame sync in normal mode or the slot in network
mode. When configured as the input flag IF1, the data value at the pin
will be stored in the IF1 bit in the SAISR register, synchronized by the
frame sync in normal mode or the slot in network mode.
Port C 1—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Signal Description
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