XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 23

• Manufacturer Part Number: XCB56362PV100
• Description: DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
• Manufacturer: Freescale Semiconductor

Specifications of XCB56362PV100

• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 33 KB
• Device Million Instructions Per Second: 100 MIPS

Freescale Semiconductor
Signal
Name
SCKR
SDO5
SCKT
SDI0
PC4
PC0
PC3
PC6
FST
Input, Output, or
Input, Output, or
Input, Output, or
Input, Output, or
Input or Output
Input or Output
Input or Output
Disconnected
Disconnected
Disconnected
Disconnected
Signal Type
Output
Input
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
State during Reset
GPIO Disconnected Frame Sync for Transmitter—This is the transmitter frame sync
GPIO Disconnected Receiver Serial Clock—SCKR provides the receiver serial bit clock
GPIO Disconnected Transmitter Serial Clock—This signal provides the serial bit rate
GPIO Disconnected Serial Data Output 5—When programmed as a transmitter, SDO5 is
DSP56362 Technical Data, Rev. 4
input/output signal. For synchronous mode, this signal is the frame
sync for both transmitters and receivers. For asynchronous mode, FST
is the frame sync for the transmitters only. The direction is determined
by the transmitter frame sync direction (TFSD) bit in the ESAI transmit
clock control register (TCCR).
Port C 4—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
for the ESAI. The SCKR operates as a clock input or output used by
all the enabled receivers in the asynchronous mode (SYN=0), or as
serial flag 0 pin in the synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is
determined by the RCKD bit in the RCCR register. When configured
as the output flag OF0, this pin will reflect the value of the OF0 bit in
the SAICR register, and the data in the OF0 bit will show up at the pin
synchronized to the frame sync in normal mode or the slot in network
mode. When configured as the input flag IF0, the data value at the pin
will be stored in the IF0 bit in the SAISR register, synchronized by the
frame sync in normal mode or the slot in network mode.
Port C 0—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
clock for the ESAI. SCKT is a clock input or output used by all enabled
transmitters and receivers in synchronous mode, or by all enabled
transmitters in asynchronous mode.
Port C 3—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
used to transmit data from the TX5 serial transmit shift register.
Serial Data Input 0—When programmed as a receiver, SDI0 is used
to receive serial data into the RX0 serial receive shift register.
Port C 6—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
Signal Description
Enhanced Serial Audio Interface
2-17