XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 51

• Manufacturer Part Number: XCB56362PV100
• Description: DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
• Manufacturer: Freescale Semiconductor

Specifications of XCB56362PV100

• Package: 144LQFP
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 100 MHz
• Ram Size: 33 KB
• Device Million Instructions Per Second: 100 MIPS

1
2
3
4
5
6
Freescale Semiconductor
149
150
151
152
153
154
155
156
No.
The number of wait states for Page mode access is specified in the DCR.
The refresh period is specified in the DCR.
The asynchronous delays specified in the expressions are valid for DSP56362.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t
read-after-read or write-after-write sequences).
BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page
access.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
Table 3-12 DRAM Page Mode Timings, Four Wait States 100 and 120MHz
Data valid to CAS assertion (write)
CAS assertion to data not valid (write)
WR assertion to CAS assertion
Last RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
Characteristics
6
DSP56362 Technical Data, Rev. 4
Symbol
t
t
WCS
t
ROH
t
t
t
DS
DH
GA
GZ
1.25 × T
3.25 × T
0.75 × T
0.5 × T
3.5 × T
4.5 × T
Expression
100 MHz:
0.25 × T
External Memory Expansion Port (Port A)
C
C
C
C
C
C
− 4.0
− 4.0
− 4.0
− 4.3
− 7.0
− 0.3
C
31.0
41.0
OFF
Min
1.0
8.2
0.0
7.2
—
—
100 MHz
1, 2, 3, 4
and not t
Max
25.5
2.5
—
—
—
—
—
—
(continued)
PC
GZ
25.2
33.5
Min
0.2
6.1
0.0
5.9
—
—
120 MHz
.
equals 3 × T
Max
20.1
2.1
—
—
—
—
—
Unit
C
ns
ns
ns
ns
ns
ns
ns
ns
3-25
for