XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 61

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XCB56362PV100

Manufacturer Part Number
XCB56362PV100
Description
DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XCB56362PV100

Package
144LQFP
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
100 MHz
Ram Size
33 KB
Device Million Instructions Per Second
100 MIPS

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Freescale Semiconductor
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2
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Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz
No.
186
187
188
189
190
191
192
193
194
195
The number of wait states for out-of-page access is specified in the DCR.
The refresh period is specified in the DCR.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
Either t
CAS assertion to data not valid (write)
RAS assertion to data not valid (write)
WR assertion to CAS assertion
CAS assertion to RAS assertion (refresh)
RAS deassertion to CAS assertion (refresh)
RD assertion to RAS deassertion
RD assertion to data valid
RD deassertion to data not valid
WR assertion to data active
WR deassertion to data high impedance
RCH
or t
RRH
Characteristics
must be satisfied for read cycles.
3
3
DSP56362 Technical Data, Rev. 4
Symbol
t
t
t
t
t
WCS
t
DHR
CSR
RPC
ROH
t
t
DH
GA
GZ
6.25 × T
9.75 × T
4.75 × T
15.5 × T
0.75 × T
9.5 × T
1.5 × T
Expression
14 × T
0.25 × T
C
C
C
C
C
C
C
C
− 5.7
− 4.3
− 4.0
− 4.0
− 4.0
− 4.0
− 4.0
− 0.3
C
External Memory Expansion Port (Port A)
151.0
90.7
Min
58.5
93.5
11.0
43.5
0.0
7.2
100 MHz
134.3
OFF
Max
2.5
and not t
125.2
Min
48.1
77.2
74.9
35.6
8.5
0.0
5.9
120 MHz
GZ
1, 2
.
111.0
(continued)
Max
2.1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3-35

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