XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 65

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XCB56362PV100

Manufacturer Part Number
XCB56362PV100
Description
DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XCB56362PV100

Package
144LQFP
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
100 MHz
Ram Size
33 KB
Device Million Instructions Per Second
100 MIPS

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Freescale Semiconductor
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External bus synchronous timings should be used only for reference to the clock and not for relative timings.
WS is the number of wait states specified in the BCR.
The asynchronous delays specified in the expressions are valid for DSP56362.
T198 and T199 are valid for Address Trace mode if the ATE bit in the OMR is set. Use the status of BR (See T212) to
determine whether the access referenced by A0–A23 is internal or external, when this mode is enabled
If WS > 1, WR assertion refers to the next rising edge of CLKOUT.
No.
CLKOUT high to RD deassertion
CLKOUT high to WR assertion
CLKOUT high to WR deassertion
Table 3-17 External Bus Synchronous Timings (SRAM Access)
Characteristics
5
DSP56362 Technical Data, Rev. 4
All frequencies:
Expression
0.5 × T
[2 ≤ WS ≤ 3]
External Memory Expansion Port (Port A)
[WS = 1 or
WS ≥ 4]
C
+ 4.3
2
,
1
3
(continued)
Min
0.0
6.3
1.3
0.0
100 MHz
Max
9.3
4.3
3.8
4.0
Unit
ns
ns
ns
3-39

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