XCB56362PV100 Freescale Semiconductor, XCB56362PV100 Datasheet - Page 72

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XCB56362PV100

Manufacturer Part Number
XCB56362PV100
Description
DSP Floating-Point 24-Bit 100MHz 100MIPS 144-Pin LQFP
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XCB56362PV100

Package
144LQFP
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
100 MHz
Ram Size
33 KB
Device Million Instructions Per Second
100 MIPS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XCB56362PV100
Manufacturer:
XILINX
0
Part Number:
XCB56362PV100
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
Parallel Host Interface (HDI08) Timing
3.11
3-46
No.
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
Read data strobe assertion width
HACK read assertion width
Read data strobe deassertion width
HACK read deassertion width
Read data strobe deassertion width
reads
HACK deassertion width after “Last Data Register” reads
Write data strobe assertion width
Write data strobe deassertion width
HACK write deassertion width
after ICR, CVR and “Last Data Register” writes
after IVR writes, or
after TXH:TXM writes (with HBE=0), or
after TXL:TXM writes (with HBE=1)
HAS assertion width
HAS deassertion to data strobe assertion
Host data input setup time before write data strobe deassertion
Host data input setup time before HACK write deassertion
Host data input hold time after write data strobe deassertion
Host data input hold time after HACK write deassertion
Read data strobe assertion to output data active from high
impedance
HACK read assertion to output data active from high impedance
Read data strobe assertion to output data valid
HACK read assertion to output data valid
Read data strobe deassertion to output data high impedance
HACK read deassertion to output data high impedance
Output data hold time after read data strobe deassertion
Output data hold time after HACK read deassertion
HCS assertion to read data strobe deassertion
HCS assertion to write data strobe deassertion
HCS assertion to output data valid
Parallel Host Interface (HDI08) Timing
5
,
6
, or between two consecutive CVR, ICR, or ISR reads
4
Characteristics
Table 3-20 Host Interface (HDI08) Timing
8
4
HACK write assertion width
4
4
8
after “Last Data Register”
DSP56362 Technical Data, Rev. 4
3
9
4
5
4
8
4
5, 6
8
4
7
8
2.5 × T
2.5 × T
Expression
T
T
C
C
+ 9.9
+9.9
C
C
+ 6.6
+ 6.6
1, 2
Min
19.9
31.6
13.2
31.6
16.5
19.9
9.9
9.9
0.0
9.9
3.3
3.3
3.3
9.9
100 MHz
Freescale Semiconductor
Max
24.2
19.1
9.9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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