IBM25PPC750FL-GR0133T IBM MICROELECTRONICS, IBM25PPC750FL-GR0133T Datasheet - Page 24

• Manufacturer Part Number: IBM25PPC750FL-GR0133T
• Description: MPU 750xx RISC 32-Bit 0.13um 600MHz 1.8V/2.5V/3.3V 750-Pin CBGA Tray
• Manufacturer: IBM MICROELECTRONICS

Specifications of IBM25PPC750FL-GR0133T

• Package: 750CBGA
• Device Core: PowerPC
• Family Name: 750xx
• Number Of Cpu Cores: 1
• Data Bus Width: 32 Bit
• Maximum Speed: 600 MHz
• I/o Voltage: 1.8|2.5|3.3 V
• Operating Temperature: -40 to 105 °C

PowerPC 750FL RISC Microprocessor
3.5 60x Bus Output ac Specifications
Table 3-9 provides the 60x bus output ac timing specifications for the 750FL microprocessor as defined and
defined in Figure 3-6 Output Timing Diagram for PowerPC 750FL RISC Microprocessor on page 26.
Table 3-9. 60x Bus Output ac Timing Specifications
Electrical and Thermal Characteristics
Page 24 of 65
Notes:
Reference
Number
1. All output specifications are measured from the VM of the rising edge of SYSCLK to the output signal level defined in Figure 3-5
2. This minimum parameter assumes CL = 0 pF.
3. t
4. Nominal precharge width for ARTRY is 1.0 t
5. Guaranteed by design and characterization and not tested.
6. Output valid timing increases as the V
7. See Section 3.6 Alternate I/O Timing for 3.3 V Bus on page 26.
8. See Table 3-2 Recommended Operating Conditions on page 17 for operating conditions.
12
13
14
15
16
17
18
19
20
Output Valid Timing Definition on page 25. Both input and output timings are measured at the pin. Timings are determined by
design.
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
SYSCLK
SYSCLK to output driven
(Output Enable Time)
SYSCLK to output valid
SYSCLK to output invalid
(Output Hold)
SYSCLK to output high
impedance (all signals
except ARTRY, ABB and
DBB)
SYSCLK to ABB and DBB
high impedance after pre-
charge
SYSCLK to ARTRY
high impedance
before precharge
SYSCLK to ARTRY pre-
charge enable
Maximum delay to ARTRY
precharge
SYSCLK to ARTRY
high impedance
after precharge
is the period of the external bus clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
Characteristic
t
SYSCLK
Minimum
DD
0.2 ×
0.3
0.5
in reduced. These values assume a minimum V
1.8 V Mode
+ 1.0
SYSCLK
Maximum
.
2.3
2.5
1.0
3.0
1.0
2.0
1, 5, 8
t
SYSCLK
Minimum
0.2 ×
0.55
0.3
2.5 V Mode
+ 1.0
Maximum
2.5
2.5
1.0
3.0
1.0
2.0
t
DD
SYSCLK
Minimum
of 1.35 V.
0.2 ×
0.55
0.3
3.3 V Mode
+ 1.0
Maximum
2.5
2.5
1.0
3.0
1.0
2.0
–
750flds60.fm.6.0
t
t
t
SYSCLK
SYSCLK
SYSCLK
Preliminary
Unit
April 27, 2007
ns
ns
ns
ns
ns
ns
2, 3, 4
Notes
2, 6
2, 7
3, 4
3, 4
3, 4