RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet

RS8234EBGC

Manufacturer Part Number

RS8234EBGC

Description

RS8234EBGC ATM XBR SAR

Manufacturer

Mindspeed Technologies

Datasheet

1.RS8234EBGC.pdf (401 pages)

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Bonase Electronics (HK) Co., Limited

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

RS8234EBGC

Manufacturer:

Quantity:

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

RS8234EBGC

Manufacturer:

MNDSPEED

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RS8234

ATM ServiceSAR Plus with xBR Traffic Management

The RS8234 Service Segmentation and Reassembly Controller integrates ATM terminal

functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service

specific functions in a single package. The ServiceSAR Controller generates and

terminates ATM traffic as well as automatically scheduling cells for transmission. The

RS8234 is targeted at 155 Mbps throughput systems where the number of VCCs is

relatively large, or the performance of the overall system is critical. Examples of such

networking equipment include Routers, Ethernet switches, ATM Edge switches, or

Frame Relay switches.

Service-Specific Performance Accelerators

The RS8234 incorporates numerous service-specific features designed to accelerate

and enhance system performance. As examples, the RS8234 implements Echo

Suppression of LAN traffic via LECID filtering, and supports Frame Relay DE to CLP

interworking.

Advanced xBR Traffic Management

The xBR Traffic Manager in the RS8234 supports multiple ATM service categories.

This includes CBR, VBR (both single and dual leaky bucket), UBR, GFR (Guaranteed

Frame Rate) and ABR. The RS8234 manages each VCC independently. It dynamically

schedules segmentation traffic to comply with up to 16+CBR user-configured

scheduling priorities for the various traffic classes. Scheduling is controlled by a

Schedule Table configured by the user and based on a user-specified time reference.

ABR channels are managed in hardware according to user programmable ABR

templates. These templates tune the performance of the RS8234’s ABR algorithms

to a specific system’s or network’s requirements

Functional Block Diagram

Data Sheet

Multi-client

PCI Bus

Master/

Slave

PCI

Counters

Timer

Proc'r

DMA

Co-

Local Memory

Segmentation

Coprocessor

CBR, VBR, ABR,

Reassembly

Interface

Coprocessor

UBR, GFR

Local Bus

Traffic Manager

Control/

Status

FIFO

Cell

RS8234

Patent Nos. 5,949,781

Distinguishing Features

Service-Specific Performance

Accelerators

• LECID filtering and echo suppression

• Dual leaky bucket based on CLP

• Frame relay DE interworking

• Internal SNMP MIB counters

• IP over ATM; supports both CLP0+1

Flexible Architectures

• Multi-peer host

• Direct switch attachment via reverse

• ATM terminal

• Optional local processor

Rx/Tx

UTOPIA

Master/Slave

(frame relay)

and ABR shaping

UTOPIA

– Host control

– Local bus control

5,768,275

5,889,779

CN8250

Device

28234-DSH-001-B

PHY

May 2003

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