CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet

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CN8237 ATM OC-12 ServiceSAR Plus with xBR Traffic Management The CN8237 Service Segmentation and Reassembly (ServiceSAR) Controller integrates ATM terminal functions, PCI Bus Master and Slave controllers, and a UTOPIA interface with service-specific functions in a single ...

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... Ordering Information Manufacturing Model Number Part Number CN8237EBGB 28237-12 Document Revision History Revision Level 100454A Advanced 100454B Advanced 100454C Advanced 500376A Advanced 28237-DSH-001-B Advanced 28237-DSH-001-C Advanced © 2003, Mindspeed Technologies, Inc. All Rights Reserved. Information in this document is provided in connection with Mindspeed Technologies™ (“Mindspeed™”) products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Except as provided in Mindspeed’ ...

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... ATM traffic. In addition, because the CN8237 buffer management and control architecture is based on Mindspeed’s 155 Mbps ServiceSAR family (Bt8233, RS8234, RS8235, and CN8236), it allows for straight-forward migration of preexisting software. Together the toolkit and architecture enable rapid prototyping and accelerate ATM system development. 28237-DSH-001-C Mindspeed Technologies ™ ...

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... Optimized for signalling address assignment • Message and streaming status modes • Raw cell mode (52 octet) • 800 Mbps half duplex Mindspeed Technologies ™ • 622 Mbps full duplex (with 2-cell PDUs) • Distributed host or SAR-shared memory reassembly • 8 programmable reassembly ...

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... Boundary scan for board-level testing • Source loopback, for diagnostics • Glueless connection to Mindspeed’s ATM physical layer devices, the RS8254/5 Standards Compliance • UNI/NNI 3.1 • TM 4.1 • Bellcore GR-1248 • ATM Forum B-ICI V2.0 28237-DSH-001-C Mindspeed Technologies ™ ...

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... Mindspeed Technologies ™ ...

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... ABR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.4 UBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.5 GFR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.5.6 xBR Cell Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.5.7 ABR Flow Control Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.6 Burst FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Implementation of OAM-PM Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.7 Standards-Based I 2-22 2.8 2.9 Electrical/Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 28237-DSH-001 1 2-1 Mindspeed Technologies ™ i ...

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... Transmit Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.2.2.5 Partial PDUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.2.6 Virtual Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.2.3 CPCS-PDU Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.3.1 AAL5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.2.3.2 AAL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.2.4 ATM PHY Layer Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 ii ATM OC-12 ServiceSAR Plus with xBR Traffic Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... AAL5 COM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3.1.2 AAL5 EOM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3.1.3 AAL5 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.2 AAL0 Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.2.1 Termination Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.2.2 AAL0 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.3 ATM Header Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 28237-DSH-001 5-1 Mindspeed Technologies ™ Table of Contents iii ...

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... Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.4.10.3 Credit Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Global Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.5 5.6 Status Queue Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.6.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.6.1.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.6.1.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.6.1.3 Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 iv ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... Rate-Shaping vs. Policing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.2.4.3 Single Leaky Bucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.2.4.4 Dual Leaky Bucket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.2.4.5 CLP-Based Buckets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.2.4.6 Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.2.4.7 Real-Time VBR and CDV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.2.5 UBR Traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.2.6 xBR Tunnels (Pipes 6-20 28237-DSH-001-C Mindspeed Technologies ™ Table of Contents v ...

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... Bucket Table for VBR2 and VBRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 6.5.4 GFR-Specific Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6.5.4.1 GFR Schedule State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 6.5.4.2 GFR MCR Limit Bucket Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 6.5.5 ABR-Specific Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 6.5.5.1 ABR Schedule State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 vi ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... Reassembly of Backward Reporting PM Cells . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.4.3.4 Turnaround and Segmentation of Backward Reporting PM Cells . . . . . . . . . . . . 7-13 7.4.3.5 Turnaround of Backward Reporting PM Cells ONLY . . . . . . . . . . . . . . . . . . . . . 7-13 7.4.4 Error Conditions During PM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.4.5 PASS_OAM Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 OAM Control and Status Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 7.5 28237-DSH-001-C Mindspeed Technologies ™ Table of Contents vii ...

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... System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Real-Time Clock Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 9.3 CN8237 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 10.0 Local Memory Interface 10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 viii ATM OC-12 ServiceSAR Plus with xBR Traffic Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... UTOPIA Configuration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4.3 UTOPIA Level 2 Multi-Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.5 UTOPIA Level 1 Mode Cell Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.6 UTOPIA Level 1 Mode Octet Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.7 Slave Level 1 UTOPIA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.8 Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 28237-DSH-001 13-1 Mindspeed Technologies ™ Table of Contents ix ...

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... CN8237 Local Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.1.3.1 Local Memory Interface Design Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.1.4 PHY Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.2 Package I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 16.3 CN8223 PHY Device Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 x ATM OC-12 ServiceSAR Plus with xBR Traffic Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16-1 Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... A-1 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 A.1 BYPASS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 A.2 A.3 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 A.4 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 A.5 Appendix B: List of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 28237-DSH-001-C Mindspeed Technologies ™ Table of Contents xi ...

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... Table of Contents xii ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... AAL5 EOM Cell Processing—Fields to Status Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Figure 5-8. AAL5 Processing—CRC and PDU Length Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Figure 5-9. AAL0 PTI PDU Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Figure 5-10. Host and SAR RSM-Shared Memory Data Structures for Scatter Method . . . . . . . . . . . . 5-13 28237-DSH-001-C Mindspeed Technologies ™ xiii ...

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... Figure 8-9. Little Endian 64-bit Master Data Transfers 8-11 Figure 8-10. Little Endian 32-bit Master Data Transfers 8-12 Figure 8-11. Little Endian SAR as Master Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 xiv ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... Interface Timing Diagram—Strobed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 Figure 16-16. RS8223 PHY Device Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 Figure 16-17. 456-Pin Ball Grid Array Package (BGA 16-22 Figure 16-18. CN8237 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 Figure A-1. Test Circuitry Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 Figure A-2. Timing Diagram A-5 28237-DSH-001-C Mindspeed Technologies ™ List of Figures xv ...

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... List of Figures xvi ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... Table 5-2. STAT Output Pin Values for BOM Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Table 5-3. Prepend Index Table Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Table 5-4. Normal VPI Index Table Entry Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 Table 5-5. VPI Index Table Entry Format with EN_PROG_BLK_SZ(RSM_CTRL1) Enabled . . . . . . . . . 5-30 28237-DSH-001-C Mindspeed Technologies ™ xvii ...

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... Bucket Table Entry Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 Table 6-16. SCH_STATE for SCH_MODE = GFR 6-48 Table 6-17. SCH_STATE Field Descriptions for SCH_MODE = GFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 Table 6-18. GFR MCR Limit Bucket Table Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 xviii ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... Table of Values for Segmentation Control Register Initialization . . . . . . . . . . . . . . . . . . . . . 15-2 Table 15-2. Table of Values for Segmentation Internal Memory Initialization 15-3 Table 15-3. Table of Values for Segmentation SAR Shared Memory Initialization . . . . . . . . . . . . . . . . . 15-4 Table 15-4. Table of Values for Scheduler Control Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . 15-6 28237-DSH-001-C Mindspeed Technologies ™ List of Tables xix ...

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... Table 16-13. Listing of Pin Numbers and Labels (Alphabetic Order 5 16-29 Table A-1. Boundary Scan Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Table A-2. IEEE Std. 1149.1 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Table A-3. Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 xx ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... This architecture lessens the control burden on the host and minimizes Peripheral Component Interconnect (PCI) bus utilization by eliminating host control activities across the PCI bus. 28237-DSH-001-C 1 (MCR) on UBR Virtual Channel Connections (VCCs) Mindspeed Technologies ™ 1-1 ...

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... The CN8237 on-chip coprocessors are surrounded by high performance PCI and UTOPIA ports that provide glueless interfaces to a variety of systems. The interfaces have full line rate throughput and low bus occupancy. 1-2 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... Mgr. Memory xBR Traffic Arbiter Manager Clock/ SEG Local Timer Memory Interface (32 bit) 67 SEG Local Memory Bus 2.0, and are fully described in succeeding chapters. Mindspeed Technologies ™ 1.0 CN8237 Product Overview RX Physical 26 FIFO RX (Depth = Port ATM 256 bytes) UTOPIA Receive Interface ...

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... The CN8237 can rate-shape ATM Adaptation Layer Type 5 (AAL5) Common Part Convergence Sublayer Protocol Data Units (CPCS-PDUs, that is, frames) in the UBR service category, by providing a guaranteed Minimal Cell Rate (MCR) for UBR VCCs. 1-4 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... ABR VCC. be tuned for different network policies. needed in local memory. congestion in the host. scheduling of a VCC whose rate has dropped below the Schedule table minimum rate. segmentation status queue for the host monitoring functions. Mindspeed Technologies ™ 1.0 CN8237 Product Overview 1-5 ...

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... CompactPCI specification. NOTE: 1-6 ATM OC-12 ServiceSAR Plus with xBR Traffic Management (This is the mode recommended by the Internet Engineering Task Force [IETF] as the most convenient model for IP over ATM interworking.) If HSWITCH* is not used, it must be tied to ground. Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... CN8237. This software is written in C, and Source code is available under license agreement. The evaluation environment also includes a full set of design schematics, and artwork for the CN8237/RS8254 EVM PCI card. 28237-DSH-001-C Mindspeed Technologies ™ 1.0 CN8237 Product Overview 1.3 Designer Toolkit 1-7 ...

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... CN8237 Product Overview 1.3 Designer Toolkit 1-8 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... Once initialized and given a segmentation or reassembly task, the CN8237 operates autonomously. Because the CN8237 is a high performance subsystem, the host/ServiceSAR architecture and the algorithms for task submission and status reporting have been optimized to minimize the control burden on the host system. 28237-DSH-001-C 2 Mindspeed Technologies ™ 2-1 ...

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... As throughput requirements escalate, the host system can add processing power in the form of additional peers. This degree of freedom creates a scalable host environment. Multiple VCCs can be assigned to each client (peer). 2-2 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

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... High Performance Host Architecture with Buffer Isolation Figure 2-1 illustrates this client/server model. The CN8237 Subsystem ATM Server LEGEND: buffer queue. illustrates the location of each queue. Mindspeed Technologies ™ 2.0 Architecture Overview ATM User-Network Interface Host Data Path Host Control/Status Flow ...

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... ATM OC-12 ServiceSAR Plus with xBR Traffic Management segmentation status queue reassembly status queue Segmentation Function (Memory) RSM/SEG Queue CN8237 Reassembly Function (Memory) Mindspeed Technologies ™ CN8237 SAR Shared Memory Areas Transmit Queues (32) Free Buffer Queues Global OAM (32) ...

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... High Performance Host Architecture with Buffer Isolation CN8237 Reassembly Block Segmentation Block Free Buffer Queues RSM/SEG Queue Global OAM Free Buffer Queue Mindspeed Technologies ™ 2.0 Architecture Overview Figure 2-3 illustrates LEGEND: Write Read xBR Scheduler Local Memory Interface (x2) ...

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... PDU. Host Memory RSM Buffer Descriptors (Write (SAR 3 Links Buffer Descriptors for the PDU.) Mindspeed Technologies ™ CN8237 PCI CN8237 RSM Coprocessor RSM Memory (Write) (Read) Free Buffer (Write) Queues (32) 8237_017 28237-DSH-001-C ...

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... The transmit queue acts as a FIFO buffer for segmentation task pointers. PCI (Read) SEG Buffer Descriptors (Write) Mindspeed Technologies ™ 2.0 Architecture Overview CN8237 SEG Coprocessor SEG Memory (Read) (Read) Transmit Queues 8237_018 ...

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... PCI Host Writes Transmit Queue Entry Host Writes SBD SAR Writes SEG Status Queue Entry Mindspeed Technologies ™ CN8237 Transmit Queues SEG Buffer Descriptors (SBD) (Buffer Descriptors Linked by Host) SEG Memory 8237_019 28237-DSH-001-C ...

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... High Performance Host Architecture with Buffer Isolation illustrates the association between the reassembly status queues PCI Host Write Free Buffer Queue Entry RSM Status Queues SAR Writes RSM Status Queue Entry Mindspeed Technologies ™ 2.0 Architecture Overview Free Buffer Queues RSM Memory 8237_020 2-9 ...

Page 44

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management illustrates the CN8237’s write-only PCI control architecture. The host PCI Control RSM Data (Writes) Status SEG Data (Read Multiples) as reads take many more clock cycles. Mindspeed Technologies ™ CN8237 CN8237 8237_021 28237-DSH-001-C ...

Page 45

... NULL adaptation layer, AAL0. 28237-DSH-001-C – word accesses for data – word accesses for control and status messages – double word accesses for data – double word accesses for control and status messages Mindspeed Technologies ™ 2.0 Architecture Overview 2.3 Automated Segmentation Engine 2-11 ...

Page 46

... ATM cell headers, but generates no other overhead fields. segmentation, wherein the segmentation coprocessor reads the entire 52-octet ATM cell from the segmentation buffer and does not generate the ATM headers for the cells. PHY interface for transmission. Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 47

... Payload Type Identifier (PTI) termination, wherein the PTI bit in the cell header is monitored for the End of Message (EOM) cell indication. Cell Count termination, wherein the CN8237 terminates the PDU when a user-defined number of cells have been received on that channel. Mindspeed Technologies ™ 2.0 Architecture Overview 2.4 Automated Reassembly Engine ...

Page 48

... PDU length for that VCC. (underflow) condition (meaning there are no available buffers in the free buffer queue that channel is assigned to). condition occurs. full (overflow) condition. Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 49

... CBR channels are given pre-assigned segmentation bandwidth, and channels for the remaining service categories scheduled according to their priority number (priority 0 being the lowest priority and priority 15 being highest). Mindspeed Technologies ™ 2.0 Architecture Overview 2.5 Advanced xBR Traffic Management Figure 2-9 ...

Page 50

... The CN8237 asynchronously multiplexes traffic based on the above schemes, as the Tx FIFO buffer empties. (2) SAR Segmentation Coprocessor (5) Start (3) Next Tx VCC ID # xBR Traffic Manager Conforming VCC ID # Schedule Table ABR Templates 16 UBR/VBR/ABR Priority Queues Mindspeed Technologies ™ CN8237 Tx FIFO Buffer To PHY Full/Empty UBR/VBR/ABR VCC ID # CBR (4) 8237_022 28237-DSH-001-C ...

Page 51

... VBR1 controls PCR and CDVT. VBR2 controls PCR and CDVT, as well as Sustained Cell Rate (SCR) and Burst Tolerance (BT). VBRC (also called VBR3) controls PCR and CDVT on all cells, but controls SCR on only CLP = 0 (that is, high priority) cells. 28237-DSH-001-C Mindspeed Technologies ™ 2.0 Architecture Overview 2.5 Advanced xBR Traffic Management 2-17 ...

Page 52

... The CN8237 implements GFR by scheduling/shaping the connections using both the VBR1 scheduling procedure (for the MCR rate value) and a UBR priority queue, thereby providing fair sharing for all GFR connections to excess bandwidth. 2-18 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 53

... Per-VCC rate control guarantees conformance to GCRA UPC/policing Dynamic reallocation of link bandwidth to active channels Dynamic, fair sharing of bandwidth on oversubscribed lines Multiple scheduling priorities Fine grained rate control Rate based on a user supplied reference clock Mindspeed Technologies ™ 2.0 Architecture Overview 2.5 Advanced xBR Traffic Management 2-19 ...

Page 54

... CONFIG1 bit 1). Two DMA slave burst FIFO buffers, (read = 8 words and write = 64 words cells) . See . Section 4.2.4 One FIFO buffer between the PHY interface and the reassembly coprocessor (64 words). illustrates the data FIFO buffer. Mindspeed Technologies ™ CN8237 ime. 28237-DSH-001-C ...

Page 55

... PM-OAM cells. 28237-DSH-001-C 16 Segmentation Controller Transmit PHY Interface FIFO 512 Reassembly Controller Receive PHY Interface FIFO PCI Slave 8 64 Mindspeed Technologies ™ 2.0 Architecture Overview 2.7 Implementation of OAM-PM Protocols Cells PHY Interface 64 8237_023 2-21 ...

Page 56

... UTOPIA and slave UTOPIA. Standard UTOPIA mode conforms to both UTOPIA Level 1 and Level 2 standards for ATM Layer devices. Slave UTOPIA mode reverses the control direction for use in place of a PHY on switch fabrics. 2-22 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 57

... Any I/O (except PCI) requiring a pullup must be tied through a resistor to 3.3 V. 2.10 Logic Diagram and Pin Descriptions A functionally partitioned logic diagram of the CN8237 is illustrated in Figure Table 28237-DSH-001-C 2-11. Pin descriptions, names, and input/output assignments are detailed in 2-1. Mindspeed Technologies ™ 2.0 Architecture Overview 2.9 Electrical/Mechanical 2-23 ...

Page 58

... AB23 HREQ* HAD45 AC24 HINTA* HAD46 R25 HSERR* HAD47 HLED* B21 HAD48 HENUM* K26 Mindspeed Technologies CN8237 I/O Address/Data Bus I/O Command/Byte Enable I/O Address/Data Command Parity upper DWORD Parity I/O Framing Signal I/O I/O Transactor Initiator Ready I/O Transaction Target Ready ...

Page 59

... PADDR4 PADDR3 PADDR2 PADDR1 PADDR0 PWNR PCS* PAS* PDS* PWAIT Input Output Open Drain Output The symbol (*) indicates active low. Mindspeed Technologies ™ 2.0 Architecture Overview 2.10 Logic Diagram and Pin Descriptions AC16 Transmit Data O AC17 AD17 AE17 AF17 AC18 AD18 ...

Page 60

... RADDR12 SADDR12 RADDR13 SADDR13 RADDR14 SADDR14 RADDR15 SADDR15 RADDR16 SADDR16 RADDR17 SADDR17 RADDR18 SADDR18 RADDR19 SADDR19 I = Input Output Open Drain Output The symbol (*) indicates active low. Mindspeed Technologies ™ CN8237 A8 I/O SEG Memory Data Bus A10 B10 C10 D10 D11 A11 ...

Page 61

... TDI Manufacturing Test TESTEN Control Signals TESTRST SCL SDA Serial EEPROM EEPWR I = Input Output Open Drain Output The symbol (*) indicates active low. Mindspeed Technologies ™ 2.0 Architecture Overview 2.10 Logic Diagram and Pin Descriptions D6 SEG Byte Write SEG Byte Write 1 B7 ...

Page 62

... ESD Protection AC8 VGG I = Input Output Open Drain Output 2-28 ATM OC-12 ServiceSAR Plus with xBR Traffic Management SPARE Spare Pins VSS Supply Power The symbol (*) indicates active low. Mindspeed Technologies ™ CN8237 SPARE_Y4 SPARE_W1 SPARE_W2 SPARE_W3 SPARE_A4 SPARE_B4 SPARE_C4 SPARE_A5 ...

Page 63

... N13 N14 N15 N16 28237-DSH-001-C VSS VSS Thermal Balls Tied to Ground I = Input Output Open Drain Output The symbol (*) indicates active low. Mindspeed Technologies ™ 2.0 Architecture Overview 2.10 Logic Diagram and Pin Descriptions P11 P12 P13 P14 P15 P16 R11 R12 ...

Page 64

... HC/BE[3:0]* lines) has been decoded and accepted as a valid reference to the target’s address space. Once asserted held by the CN8237 (when acting as a slave) until HFRAME* is deasserted; otherwise, it indicates (in conjunction with HSTOP* and HTRDY*) a target abort. Mindspeed Technologies ™ CN8237 Definition 28237-DSH-001-C ...

Page 65

... open drain. Logic low turns on LED. Compact PCI hot swap signal open drain. Compact PCI hot swap signal. Driven by master requesting 64-bit transfer. I/O Mindspeed Technologies ™ 2.0 Architecture Overview 2.10 Logic Diagram and Pin Descriptions Definition 2-31 ...

Page 66

... FIFO buffer in the CN8237 is full. I/O In UTOPIA mode, RxEN* indicates that the CN8237 is ready to receive data on the RxDATA[15:0], RxPAR, and RxSOC (RxMARK) lines in the next clock cycle. This pin is an output in UTOPIA mode and an input in slave UTOPIA mode. Mindspeed Technologies ™ CN8237 Definition 28237-DSH-001-C ...

Page 67

... Interface clock to PHY device. PHY Device Data Bus. I/O I PHY device interrupt signal. Asserted by the CN8237 whenever the HRST* input is O asserted. Externally generated signal to extend PHY device I accesses. Mindspeed Technologies ™ 2.0 Architecture Overview 2.10 Logic Diagram and Pin Descriptions Definition 2-33 ...

Page 68

... RCLK0; it can be used for the UTOPIA interface clock. O CN8237 internal status outputs. Internal status controlled by the STAT_MODE[4:0] field in the CONFIG0 Register. I User-defined general purpose input. This value is reflected in HOST_ISTAT0 bit 31, GPI. I External Scheduler Reference Clock. If not used, must be grounded. Mindspeed Technologies ™ CN8237 Definition — 28237-DSH-001-C ...

Page 69

... Enables Electrostatic Discharge (ESD) protection. When the SAR is connected to 3.3 V power supply yet there are 5 V devices on the board, tie this pin for ESD Protection. Otherwise, tie to 3.3 V. Mindspeed Technologies ™ 2.0 Architecture Overview 2.10 Logic Diagram and Pin Descriptions Definition ...

Page 70

... Architecture Overview 2.10 Logic Diagram and Pin Descriptions 2-36 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 71

... The CN8237 provides a flexible, high performance host interface architecture. With this interface, the CN8237 facilitates a scalable, distributed host system. The interface also minimizes the impact of an ATM port on the host system’s PCI bus. 28237-DSH-001-C 3 APPLICATION EXAMPLE Mindspeed Technologies ™ 3-1 ...

Page 72

... ATM services. 3-2 ATM OC-12 ServiceSAR Plus with xBR Traffic Management CN8237 Subsystem PCI Interface LEGEND: Figure 3-1, the clients need not be physically distinct PCI peers. The Mindspeed Technologies ™ CN8237 Figure 3-1 illustrates this ATM Server ATM User-Network Interface ...

Page 73

... PCI memory space. The host defines the address range of each peer. The CN8237 transfers data within this address range. An address range corresponds either to a region of centralized host memory set of peer resident buffers. 28237-DSH-001-C Mindspeed Technologies ™ 3.0 Host Interface 3.2 Multiple Client Architecture ...

Page 74

... Centralized memory 1 PCI BUS 2 1 PCI Host LEGEND: Centralized Memory PCI Motherboard defines the CN8237 control and status queues. Type Segmentation Transmit queue Control Segmentation status queue Status Mindspeed Technologies ™ CN8237 CN8237 PCI Transaction Peer-to-Peer Transaction # # ...

Page 75

... Number of queue entries processed by SAR before writing READ_UD Number of queue entries since last write of READ_UD SAR pointer to READ_UD illustrates the control queue management algorithm. The host Mindspeed Technologies ™ 3.0 Host Interface 3.3 Write-only Control and Status Location Initialization Host variable 0 ...

Page 76

... SAR initiates EPD on all channels assigned to this queue. describes SAR handling of free buffer queue underflow in detail. 3-6 ATM OC-12 ServiceSAR Plus with xBR Traffic Management VLD bit Update Host Y UPDATE= UPDATE=0 INTERVAL READ_UD_PNTR= READ N Mindspeed Technologies ™ CN8237 Base Register READ++ UPDATE++ (Base Table) 8237_026 Chapter 5.0 28237-DSH-001-C ...

Page 77

... READ_UD Number of queue entries since last write of READ_UD Host pointer to READ_UD illustrates the status queue management algorithm. The host initializes Table 3-3. Mindspeed Technologies ™ 3.0 Host Interface 3.3 Write-only Control and Status Location Initialization SAR Base table 0 SAR Base table ...

Page 78

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management VLD bit Update SAR Y UPDATE= UPDATE=0 INTERVAL READ_UD_PNTR= READ N PCI Bus Boundary Mindspeed Technologies CN8237 READ_UD_PNTR READ_UD (Base Table) WRITE++ (Base Table WRITE = Signal READ_UD - 1 Overflow Chapter 4.0 and Chapter 5.0 ™ 28237-DSH-001-C ...

Page 79

... STAT_CNT, the interrupt window is opened, which allows the interrupt to propagate to the output pin. The counter is reset when the status registers are read and the interrupt output goes inactive. 28237-DSH-001-C Mindspeed Technologies ™ 3.0 Host Interface 3.3 Write-only Control and Status ...

Page 80

... Host Interface 3.3 Write-only Control and Status 3-10 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 81

... Due to the large number of specified parameters for ABR traffic, ABR VCCs occupy two descriptors (20 words) in the Segmentation VCC table. The VCC_INDEX for ABR VCCs points to the first of the two descriptors, and must be evenly divisible by two. 28237-DSH-001-C 4 Mindspeed Technologies ™ 4-1 ...

Page 82

... VCC table with a CBR VCC at VCC_INDEX 3, an ABR VCC Table VCC_INDEX = 0x0 } 10 Words = 1 Descriptor } (CBR VCC) 7 Words VCC Table Entry } 3 Words SCH_STATE } VCC Table Entry 7 Words } SCH_STATE 13 Words VCC Table Entry SCH_STATE Mindspeed Technologies ™ CN8237 } 1 Descriptor } 2 Descriptors 8237_028 28237-DSH-001-C ...

Page 83

... VCC_INDEX, defined as the offset into the table in 10-word increments, uniquely identifies a segmentation channel. In all communication between the SAR and the host, a VCC_INDEX field specifies a VCC. 28237-DSH-001-C Section 4.3.1 for full details of the structure of a Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.2 Segmentation Functional Description 4-3 ...

Page 84

... Buffer contains complete message. Restart/terminate CPCS-PDU. 4-4 ATM OC-12 ServiceSAR Plus with xBR Traffic Management SAR SEG-shared memory data buffer segmentation should be limited to low bandwidth applications, such as Signalling, OAM, and ILMI. Buffer to Message Adaptation Mindspeed Technologies ™ CN8237 Table 4-1 describes 28237-DSH-001-C ...

Page 85

... SBD chaining. The host has formed a Host (or SAR SEG-Shared) Memory Section 3.3.1. The host processor writes a Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.2 Segmentation Functional Description ...

Page 86

... SBDs to a VCC table entry. As the new buffers are submitted, the VCC is processing a single buffer PDU (BOM/EOM). The CN8237 accepts new PDUs while it is processing outstanding buffers. BUFF_PNTR = &A BUFF_PNTR = &B BUFF_PNTR = &C BUFF_PNTR = &Z Mindspeed Technologies ™ CN8237 SBDs VCC_INDEX = 4 CONTROL <BOM> NEXT ...

Page 87

... VCC_INDEX (that is, the same VCI) for the length of the PDU. This allows the CN8237 to multiplex VCI messages at the PDU level. For AAL5 segmentation, the host must guarantee that SBDs are linked with PDU multiplexing to preserve CPCS-PDU integrity. 28237-DSH-001-C BD_PNTR Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.2 Segmentation Functional Description VCC_INDEX = 4 CONTROL < ...

Page 88

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management illustrates the CN8237’s AAL5 PDU generation scheme. The SAR USER DATA BUFFER(S) H (Set PTI[ ATM_HEADER Internal CRC Accumulator Circuits SEG VCC Table Entry Mindspeed Technologies CN8237 Chapter 7.0 covers H PAD UU CPI LEN CRC-32 UU PDU_LEN CRC_REM ™ ...

Page 89

... SBD. USER_PNTR may contain the address of the buffer host data structure describing the buffer. To simplify host management, the CN8237 also returns the VCC_INDEX of the VCC on which the buffer was transmitted. 28237-DSH-001-C Section Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.2 Segmentation Functional Description Section 6.2.3.3 discusses this 3 ...

Page 90

... AAL5-AAL0 VCC table entries. Table 4-2. Segmentation VCC Table Entry—AAL5-AAL0 Format ( Word PM_INDEX 1 UU PORT_ID 2 3 PDU_LEN 4 4-10 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Tables 4-2 LAST_PNTR BOM_PNTR ATM_HEADER CRC_REM Mindspeed Technologies ™ CN8237 and 4-3 describe the BUFFER_LEN 28237-DSH-001-C ...

Page 91

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management Table 4-2. Segmentation VCC Table Entry—AAL5-AAL0 Format ( Word STAT 6 7-9/19 KEY: = Written by host at VCC setup = May be dynamically modified during active segmentation 28237-DSH-001-C 4.3 Segmentation Control and Data Structures CURR_PNTR SCH_STATE Mindspeed Technologies ™ 4.0 Segmentation Coprocessor NEXT_VCC 4-11 ...

Page 92

... VCC set to zero by the SAR when the data available for the VCC is not sufficient to send at entire ATM cell. NX_EOM Indicates that the next cell is the end of a CPCS-PDU. 4-12 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Description Chapter 7.0.) Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 93

... AAL5-AAL0 format. 28237-DSH-001-C 4.3 Segmentation Control and Data Structures Description Chapter 6.0 for details.) shows the format for Virtual FIFO buffer VCC table entries, Table 4-5 Mindspeed Technologies ™ 4.0 Segmentation Coprocessor describes the field that 4-13 ...

Page 94

... Field Name FIFO_PNTR Pointer to the PCI space data FIFO buffer for CBR_FIFO scheduling mode. Reserved Always set to 0. 4-14 ATM OC-12 ServiceSAR Plus with xBR Traffic Management LAST_PNTR BOM_PNTR ATM_HEADER FIFO_PNTR CRC_REM CURR_PNTR= 0x00000 SCH_STATE Description Mindspeed Technologies ™ CN8237 Reserved 28237-DSH-001-C ...

Page 95

... This definition of bits 31:16, MISC_DATA field, applies when the RPL_VCI bit is set; used when identifying virtual channels NOTE(S): under a VP VCC. 28237-DSH-001-C through 4-9 describe the entry formats and field definitions for the NEXT_PNTR USER_PNTR BUFFER_PNTR Reserved Reserved NEW_VCI Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.3 Segmentation Control and Data Structures Rsvd LENGTH SEG_VCC_INDEX PTI_DATA VCI_DATA 4-15 ...

Page 96

... Controls AAL segmentation mode AAL5 01 = AAL0 Read 48-octet ATM cell payload from segmentation buffer. Only formatting is to set PTI[0] on last cell of an EOM buffer Reserved 11 = Reserved 4-16 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Description Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 97

... Identifies the VCC entry in the VCC table. The CN8237 links this buffer descriptor to the identified VCC. Reserved Always set to 0. 28237-DSH-001-C 4.3 Segmentation Control and Data Structures Description Table 4-1.) Table 4-1.) Chapter 7.0.) Mindspeed Technologies ™ 4.0 Segmentation Coprocessor Chapter 7.0. 4-17 ...

Page 98

... Reserved Always set to 0. 4-18 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Tables 4-10, 4-11, and SEG_BD_PNTR Reserved SEG_BD_PNTR Reserved (Must be Written) Description Mindspeed Technologies ™ CN8237 4-12 describe the format of these Rsvd Rsvd 28237-DSH-001-C ...

Page 99

... READ_UD_PNTR (TxQ) 64-Bit Value Access XXXX First Word First Word XXXX Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 4.3 Segmentation Control and Data Structures 4-13, 4-14, and 4-15 below describe 32-Bit Access 31 0 First Word XXXX 31 0 XXXX First Word 8237_158 4-19 ...

Page 100

... Reserved Description Chapter 2.0 for details.) Read Update will be written cross-reference between the routing tag table and the The maximum TxFIFO size is reduced when using routing tags. See Table 4-16. Mindspeed Technologies ™ CN8237 READ READ Figures 4-7 through 4-9 show the ...

Page 101

... Table 4-16. Maximum TxFIFO Size with Routing Tags Tag Size Figure 4-7. Route Tag Table for tag_size = 2 and 4 SEG_TAGBASE(SEG_TAGB) seg_vcc_index TXFIFO 28237-DSH-001-C 4.3 Segmentation Control and Data Structures TxFIFO (Maximum Number Of Cells ATM header Mindspeed Technologies ™ 4.0 Segmentation Coprocessor 0 h3 8237_034 4-21 ...

Page 102

... Figure 4-9. Route Tag Table for tag_size = 10 SEG_TAGBASE(SEG_TAGB) seg_vcc_index TXFIFO 4-22 ATM OC-12 ServiceSAR Plus with xBR Traffic Management 0x0 0x4 ATM header 0x0 0x4 b8 b9 b10 b11 0x8 b10 b11 ATM header Mindspeed Technologies ™ CN8237 b3 h3 8237_035 b7 h3 8237_036 28237-DSH-001-C ...

Page 103

... Segmentation Control and Data Structures Table 4-23. Refer to Section 6.3.7.5 for a description of the trigger mechanism for MSTR_CTRL_DWORD must be set to 1. Mindspeed Technologies ™ 4.0 Segmentation Coprocessor b10 b11 t10 4-18, 4-19, and 4-20 describe the Tables 4-21, 4-22, and 4-23 ...

Page 104

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management Segmentation (Status Queue Entry) 64-Bit Access First Word Second Word Second Word First Word USER_PNTR Reserved USER_PNTR Reserved Mindspeed Technologies ™ CN8237 32-Bit Access 0 31 Second Word First Word 31 0 First Word Second Word 8237_157 SEG_VCC_INDEX SEG_VCC_INDEX 28237-DSH-001-C ...

Page 105

... Segmentation VCC index on which the SAR transmitted the buffer or PDU. Reserved Always set to 0. Table 4-21. Segmentation Status Queue Format for ACR/ER (64-bit) Word 28237-DSH-001-C 4.3 Segmentation Control and Data Structures Description Chapter 6.0.) Chapter 6.0.) Reserved Mindspeed Technologies ™ 4.0 Segmentation Coprocessor ACR SEG_VCC_INDEX 4-25 ...

Page 106

... The status queue base table entry contains all of the SAR’s write-only control variables. Tables 4-26 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Reserved Description 4-24, 4-25, and 4-26 describe the format of these entries. Mindspeed Technologies ™ CN8237 ACR SEG_VCC_INDEX 28237-DSH-001-C ...

Page 107

... READ_UD pointer in the base table register, the CN8237 inhibits segmentation on all channels that report on the overflowed status queue. All other channels are unaffected. 28237-DSH-001-C 4.3 Segmentation Control and Data Structures BASE_PNTR WRITE Reserved BASE_PNTR WRITE Reserved Description Mindspeed Technologies ™ 4.0 Segmentation Coprocessor READ_UD READ_UD 4-27 ...

Page 108

... SRAM is in the address Description Status Queue 0 Base Table Status Queue 1 Base Table Status Queue 31 Base Table Transmit Queue 0 Base Table Transmit Queue 1Base Table Transmit Queue 31Base Table Not implemented Initialize to 0xFFFFFFFF Not implemented Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 109

... ATM, the cell contained in any incoming cell slot can belong to any VCC. Thus, the reassembly coprocessor must assign each arriving cell to the proper VCC, thereby demultiplexing the incoming messages. Figure 5-1 28237-DSH-001-C 5 illustrates the basic reassembly process flow. Mindspeed Technologies ™ Chapter 6.0 5-1 ...

Page 110

... K VCC indexes, the actual number of reassembly VCCs allowed by the SAR is limited by the amount of SAR RSM-shared memory available in which to allocate and create RSM VCC tables, free buffer queues, etc. 5-2 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Messages Reassembly Coprocessor Mindspeed Technologies ™ CN8237 Host (64 K) 8237_037 28237-DSH-001-C ...

Page 111

... VCC. 28237-DSH-001-C illustrates how entries in the RSM VCC table are indexed by Reassembly VCC Table VCC_INDEX = Words = 1 Descriptor VCC_INDEX = 4 VCC Table Entry VCC Table Entry VCC_INDEX = 0xFFFF (64 k VCCs) Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.2 Reassembly Functional Description 8237_038 5-3 ...

Page 112

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management illustrates the direct index channel lookup mechanism. RSM_TBASE (RSM_VCCB) VCI Index Table (for one VPI) VCI [15:6] VCC_Block_Index (Max. 1024 entries for each VPI) Mindspeed Technologies ™ CN8237 VCC Table (Block of 64 VCC Table Entries) VCI [5:0] 8237_039 28237-DSH-001-C ...

Page 113

... VCI[15:0] 65536 VCI[15:1] 32768 VCI[15:2] 16384 VCI[15:3] 8192 VCI[15:4] 4096 VCI[15:5] 2048 VCI[15:6] 1024 Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.2 Reassembly Functional Description Section 5.7.1. Reassembly VCC Table VCI [x-1:0] (For x=0, pointer is not applicable) Where x = value of VCI_IT_BLK_SZ 8237_040 Number of ...

Page 114

... VC_EN allows idle cells to be filtered if the PHY layer has not already done so. If the channel is active, the CN8237 increments the CELL_RCVD_CNT counter. 5-6 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Section 5.2.2.2, by setting EN_PROG_BLK_SZ(RSM_CTRL1) VCI_IT_PNTR VCI[15: VCC_INDEX = VCC_BLOCK_INDEX + VCI[x-1:0] Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 115

... CONFIG1(NUM_PORTS), their VPI_SIZE entry 1024 entries PORT_ID = 0 (MAX_VPI = 1023) 512 entries PORT_ID = 1 (MAX_VPI = 511) PORT_ID = 2 (turned off) 1024 entries PORT_ID = 3 (MAX_VPI = 1023) 2048 entries PORT_ID = 4 (MAX_VPI = 2047) Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.3 CPCS-PDU Processing Figure 5-5 shows 8237_042 5-7 ...

Page 116

... CN8237 to perform specific functions as described throughout this chapter. 5-8 ATM OC-12 ServiceSAR Plus with xBR Traffic Management illustrates the basic process function. COM Cells . . . . . . (Hdr) (Payload) Mindspeed Technologies ™ CN8237 EOM Cell (Hdr) (Payload 8237_043 28237-DSH-001-C ...

Page 117

... LENGTH field in the trailer of the AAL5 PDU. If the number of PAD bytes is less than 0 or greater than the 47 the reassembly coprocessor sets, the PAD_ERROR bit in the status queue entry to a logic high. status queue entry is set to a logic high. buffer(s) in memory. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.3 CPCS-PDU Processing Status ...

Page 118

... CRC-32 (Not Null) (Pad Check) (Compare) Section min[RSM_CTRL0(MAX_LEN) x 1024, 65568] TOT_PDU_LEN + 48 MAX_LEN Section 5.4.7, for details on how this process is handled. TOT_PDU_LEN + 48 MAX_LEN Mindspeed Technologies ™ CN8237 RSM VCC Table Entry Status Queue Entry 8237_045 5.6, for full details. 1024 (or 65568) × ...

Page 119

... AAL0 PDU in this mode is (CCOUNT × 2) bytes. provides an illustration of this. (Hdr) (Payload) PTI[0]=0 Section TOT_PDU_LEN + 48 > CCOUNT × 2, TOT_PDU_LEN + 48 > CCOUNT × 2, Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.3 CPCS-PDU Processing (EOM Cell (Hdr) (Payload) PTI[0]=1 ...

Page 120

... When RSM_CTRL0(PREPEND_INDEX logic high, the VCC_INDEX is appended to the BOM cell as follows: Table 5-3. Prepend Index Table Format Word Reserved 5-12 ATM OC-12 ServiceSAR Plus with xBR Traffic Management CPCS-PDU. Table 5-2. STAT[ Mindspeed Technologies ™ CN8237 STAT[ VCC_INDEX 28237-DSH-001-C ...

Page 121

... PCI bus between host and local systems. HOST SAR RSM-Shared Free Buffer Queues Cell Buffers Free Buffer Queue Base Table (Inside the CN8237) Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management Figure 5-10: two in the 8237_048 5-13 ...

Page 122

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management FBQx_BASE + [(size of each free buffer queue) x BFRx MOD 16] (index of first entry for the queue) + [(READ index pointer) x (size of each free buffer queue entry)] Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 123

... BFRx (BFR0 or BFR1) READ 28237-DSH-001-C illustrates this structure. Refer to Free Buffer Queue Bank (SAR RSM-Shared Memory) [BFRx x (Global size of FBQ)] (16 Free Buffer Queues in Each Bank) Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management Chapter 3.0, for more FBQx_BASE 8237_049 5-15 ...

Page 124

... VCC table entry for that channel is a logic low. NOTE: 5-16 ATM OC-12 ServiceSAR Plus with xBR Traffic Management illustrates this structure. For more information about big and little endian processing, refer to Section 8.4. Mindspeed Technologies ™ CN8237 Buffers (Host Memory) 8237_050 28237-DSH-001-C ...

Page 125

... For each unallocated free buffer queue entry, write the VLD bit to a logic low. 5.4.4.4 Other The user can globally disable free buffer underflow protection by setting Initialization RSM_CTRL(RSM_FBQ_DIS logic high. 28237-DSH-001-C Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management 5-17 ...

Page 126

... VLD bit set to a logic high, the reassembly coprocessor automatically recovers from the empty condition. 5-18 ATM OC-12 ServiceSAR Plus with xBR Traffic Management 5.4.6.) If the VLD bit is a logic high, the reassembly coprocessor uses the Mindspeed Technologies ™ CN8237 Section 5.4.7. Also ...

Page 127

... VCC table. All cells on that channel up to the next BOM are discarded. entry for this channel will be set to a logic high. The CNT_ROVR bit in the VCC table holds this flag information until a status is sent. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5 ...

Page 128

... Non-EOM Max PDU Length exceeded • Free buffer queue underflow • Status queue overflow 5-20 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Avoid having the Status Queue Overflow (or Full Condition) and DMA FIFO Buffer Full conditions at the same time. Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 129

... In AAL5 and AAL0, PTI termination modes, the reception of a non-EOM cell resets the counter. 28237-DSH-001-C GTO_EN set to 0 resets the internal time-out interrupt counter. 5.4.8.4. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management 5-21 ...

Page 130

... FIFO buffer. External circuitry must also ensure that only complete cells are written into the host FIFO buffer. The beginning of a cell transfer can be detected by the PCI address being 64-byte aligned. 5-22 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Period = SYSCLK period x RSM_TO_PER x RSM_TO_CNT x TERM_TOCNTx Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 131

... VCC table(s) still decrements each time the VCC receives a BOM cell. The RX_COUNTER should not be decremented when the FBQ is empty. There is no workaround for this problem. The user “must” avoid FBQ empty conditions when firewalling is enabled. channel. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.4 Buffer Management 5-23 ...

Page 132

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management channels. This includes idle cells, since those channels will be turned off. channel firewall, buffer queue underflow, FIFO buffer full packet discard, status queue overflow, or maximum CPCS-PDU length exceeded on non-EOM cells. Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 133

... RSM-shared memory, and allows for independent circular status queues. Figure 5-13. Data Structure Locations for Status Queues 28237-DSH-001-C HOST SAR RSM-Shared Status Queue Base Table (Inside the CN8237) Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.6 Status Queue Operation Figure 5-13: one in host 8237_051 ...

Page 134

... Figure 5-14. Status Queue Structure Format Status Queue Base Table (Internal SRAM) 0x1000 STAT (From RSM VCC BASE_PNTR Table Entry) WRITE (32 entries in the base table) 5-26 ATM OC-12 ServiceSAR Plus with xBR Traffic Management illustrates this structure. (32 Status Queues) Mindspeed Technologies ™ CN8237 8237_052 28237-DSH-001-C ...

Page 135

... CPCS-PDU, with EOM bit a logic high, contains valid status data for that PDU. Refer to queues. 28237-DSH-001-C BASE_PNTR field. Chapter 2.0, for more detailed information on the operation of status Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.6 Status Queue Operation 5-27 ...

Page 136

... Again, the host periodically writes the current READ index value into the READ_UD field of the status queue base table entry. 5-28 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Section 3.3.2.4 for alternative methods. Only status queues 0 through 15 are reported in this register. Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 137

... VPI/VCI value. mechanism. 28237-DSH-001-C Avoid having the Status Queue Overflow (or Full Condition) and DMA FIFO Buffer Full conditions at the same time. Figure 5-15 Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures illustrates this lookup 5-29 ...

Page 138

... VPI Index table format (one word per entry) describes the VPI Index table format (two words per entry) with describes the field definitions for the VPI Index table fields. Description/Function Mindspeed Technologies ™ CN8237 VCI Index Table (For One VPI) ...

Page 139

... Reassembly Control and Data Structures Description/Function describes the VCI Index table format without the programmable VCC describes the VCI Index table format with EN_PROG_BLK_SZ describes the VCI Index table Descriptions. VCC_BLOCK_INDEX Description/Function Mindspeed Technologies ™ 5.0 Reassembly Coprocessor Reserved VCC_BLOCK_INDEX 5-31 ...

Page 140

... Figure 5-16 continuation from Figure 5-16. Reassembly VCC Table Entry Lookup Mechanism Base Register RSM_TBASE(RSM_VCCB) VCC_BLOCK_INDEX 5-32 ATM OC-12 ServiceSAR Plus with xBR Traffic Management illustrates the VCC table entry lookup mechanism as a Figure 5-15. VCI[5:0] Mindspeed Technologies ™ CN8237 8237_054 28237-DSH-001-C ...

Page 141

... AAL0 RSM VCC table entries. PM_INDEX Reserved Reserved CRCREM STAT CBUFF_PNTR BOM_BD_PNTR CURR_BD_PNTR ERS_INDEX D_NCR_HI_MANT Rsvd D_NCR_LO_EXP Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures AAL_EN ABR_CTRL TOT_PDU_LEN BFR1 BFR0 Rsvd SERV_DIS RX_COUNTER/VPC_INDEX EXP_TA_ER ...

Page 142

... Reserved 10 Reserved CONG_ID 11 Rsvd D_NCR_HI_EXP 5-34 ATM OC-12 ServiceSAR Plus with xBR Traffic Management PM_INDEX Reserved Reserved STAT CBUFF_PNTR BOM_BD_PNTR CURR_BD_PNTR ERS_INDEX D_NCR_HI_MANT Rsvd D_NCR_LO_EXP Mindspeed Technologies ™ CN8237 AAL_EN ABR_CTRL TOT_PDU_LEN TCOUNT BFR1 BFR0 Rsvd SERV_DIS RX_COUNTER/VPC_INDEX EXP_TA_ER D_NCR_LO_MANT 28237-DSH-001-C ...

Page 143

... If set high, all 52 octets of the cell are written to a cell buffer. = Enable interrupt after BOM buffer filled in Message Mode. = Enable LANE-LECID echo suppression. = Enable frame relay DE (Discard Eligibility) mode. = Enable CLP discard mode. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures 3 ...

Page 144

... SAR maintains this bit. = Active PDU. Indication that at least one buffer has been taken off of the free buffer queue for the current PDU being received. = BOM buffer flag. Set high when filling the first buffer of a PDU. Mindspeed Technologies ™ CN8237 3 ...

Page 145

... During initialization in each buffer descriptor entry, the host writes a pointer to an associated reassembly data buffer, in the BUFF_PTR field. Tables 5-13 NOTE: 28237-DSH-001-C Description/Function and 5-14 describe the format of the reassembly buffer descriptors. MSTR_CTRL_DWORD must be set to 1. Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures 5-37 ...

Page 146

... Value Access XXXX First Word First Word XXXX BUFF_PTR NEXT_PTR Description/Function The SAR does not access this word; the user may place it anywhere in the buffer Mindspeed Technologies CN8237 32-Bit Access First Word XXXX XXXX First Word 8237_159 000 ™ 28237-DSH-001-C ...

Page 147

... READ_UD_PNTR (FBQ) 64-Bit Access First Word XXXX First Word XXXX XXXX First Word XXXX First Word UPDATE Reserved Reserved READ_UD_PNTR Reserved Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures 32-Bit Access 0 0 8237_160 READ FORWARD Reserved 5-39 ...

Page 148

... Forward Valid. If logic high, word contains valid buffer return information. VCC_INDEX Channel of corresponding buffer return. 5-40 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Description/Function and 5-18 describe the format of the free buffer queue entries. BUFFER_PNTR BD_PNTR Not Used Description/Function 0 . Mindspeed Technologies ™ CN8237 Rsvd VCC_INDEX 28237-DSH-001-C ...

Page 149

... Second Word Third Word Fourth Word Second Word First Word Fourth Word Third Word BASE_PNTR WRITE Reserved Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures 32-Bit Access 31 0 Second Word First Word Fourth Word Third Word 31 0 First Word ...

Page 150

... OVFL CNT_ROVR are defined in NOTE(S): 5-42 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Description/Function BD_PNTR CPI STATUS BD_PNTR BIPV Table 5-26 under “Status.” Mindspeed Technologies ™ CN8237 000 CPCS_LENGTH VCC_INDEX OAM STM 000 TRCC0+1 VCC_INDEX Rsvd OAM STM ...

Page 151

... FFPD EPD Table 5-27. STM Field Bits Bit 28237-DSH-001-C BD_PNTR Reserved BIPV UNDF OVFL SFPD 3 2 EOM BOM Mindspeed Technologies 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures 000 TRCC0+1 VCC_INDEX Rsvd OAM STM A3L2_ERR ABORT CNT_ROVR 1 0 STM_MODE BFR1 ™ ...

Page 152

... F5 OAM End to End 110 = PTI = 6 111 = PTI = 7 5-44 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Description/Function 0 . EPD FW UNDF OVFL due to firewall, buffer underflow, LI_EPD, SN_EPD, ST_EPD, CLP discard or Max PDU length exceeded. Mindspeed Technologies ™ CN8237 SFPD TO ABORT CNT_ROVR 28237-DSH-001-C ...

Page 153

... BOM STM_MODE an EOM. BOM. In Message Mode with BOM interrupt enabled, indicates that status entry points to only one buffer which contains a BOM. indicates COM(BFR1), logic low indicates BOM(BFR0). Mindspeed Technologies ™ 5.0 Reassembly Coprocessor 5.7 Reassembly Control and Data Structures BFR1 5-45 ...

Page 154

... LANE traffic on the ATM network. 5-46 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Figure 5-20 (Table holds 32 LECIDs) DPRI LECIDn+ LECIDn+ (etc.) Function/Description Mindspeed Technologies ™ CN8237 includes unique identifiers Tables 5-29 and 5-30 display the LECIDn LECIDn+ (etc.) ...

Page 155

... Field Name TERM_TOCNTx Time-Out expiration count. TO_VCC_INDEX Time-Out VCC_INDEX tracking variable. 28237-DSH-001-C 5.7 Reassembly Control and Data Structures Section 5.4.8. Tables 5-31 Description/Function Mindspeed Technologies ™ 5.0 Reassembly Coprocessor and 5-32 display the entries and TERM_TOCNT0 TERM_TOCNT2 TERM_TOCNT4 TERM_TOCNT6 TO_VCC_INDEX 5-47 ...

Page 156

... Reassembly Internal SRAM is in the address Description Status Queue 0 Base Table Status Queue 1 Base Table Status Queue 31 Base Table Free Buffer Queue 0 Base Table Free Buffer Queue 1 Base Table Free Buffer Queue 31 Base Table Other Internal Reassembly Registers: Global Time-Out Table Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 157

... CN8237 supports these for each service category. The shaded areas do not indicate that the service category and attribute are undefined for the SAR—they indicate that the TM 4.1 specification does not detail them. 28237-DSH-001-C 6 provides a list of ATM attributes detailed in the TM 4.1 specification (that Mindspeed Technologies ™ 6-1 ...

Page 158

... CBR rt-VBR nrt-VBR — Specified/Supported Supported Supported — Supported — Supported — — — Supported (4) Supported (4) Supported — — Mindspeed Technologies ™ CN8237 (3) UBR ABR GFR — — — Supported — (4) Not Supported Not (4) Not Supported (4) (4) Supported Supported Supported — ...

Page 159

... VCCs assigned to a single CBR scheduling priority, with individual VCCs within that tunnel scheduled based on their traffic parameters. Traffic into this CBR tunnel can be of types UBR, VBR and ABR. To enhance flexibility, the CN8237 supports 16 priorities of non-CBR traffic. 28237-DSH-001-C Mindspeed Technologies ™ 6.0 Traffic Management 6.1 CN8237 Overview 6-3 ...

Page 160

... System Cell Scheduler Clock Per-VCC Parameters and Priority 6-4 ATM OC-12 ServiceSAR Plus with xBR Traffic Management shows a high-level block diagram of the Cell Scheduler control VCC_INDEX Segmentation Coprocessor Mindspeed Technologies ™ CN8237 CBR VBR UBR GFR ATM Network 8237_056 28237-DSH-001-C ...

Page 161

... Cell Scheduler Manager RATE UPDATE 28237-DSH-001-C Dynamic Schedule Table VCC_INDEX Segmentation Coprocessor Per-VCC Parameters and Priority Reassembly Coprocessor Mindspeed Technologies ™ 6.0 Traffic Management 6.1 CN8237 Overview Figure 6-2 shows a high level block ABR Cell Stream ATM Network RM Cell Feedback 8237_057 6-5 ...

Page 162

... Dynamic Schedule table each channel is assigned. 6-6 ATM OC-12 ServiceSAR Plus with xBR Traffic Management 1. Thus, separate templates would Section 6.2.5. By configuring the number of slots and the duration Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 163

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management The scheduler clock is selected by bit 26 (USE_SCHREF) of the SCH_CTRL register, as shown in Table 6-2. Scheduler Clock Selection 28237-DSH-001-C Table 6-2. USE_SCHREF Scheduler Clock 0 SYSCLK 1 SCHREF Mindspeed Technologies ™ 6.0 Traffic Management 6.2 xBR Cell Scheduler Functional Description 6-7 ...

Page 164

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management represents an example of a schedule table. In this example, the Current Cell Scheduler Postion Increments Postition by One Entry Each SLOT_PER SCHEDULE TABLE Mindspeed Technologies ™ CN8237 Assigned VCC_INDEX(es) SLOT INDEX } One to Eight Words 29 SCHEDULE SLOT 8237_058 28237-DSH-001-C ...

Page 165

... Mindspeed Technologies ™ 6.0 Traffic Management Available VBR/ABR Priority Levels (1) 0–15 (1) 1–15 VBR_OFFSET + 0–13 VBR_OFFSET + 1–13 VBR_OFFSET + 0–11 VBR_OFFSET + 1–11 VBR_OFFSET + 0–9 VBR_OFFSET + 1–9 VBR_OFFSET + 0–7 VBR_OFFSET + 1–7 VBR_OFFSET + 0– ...

Page 166

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management illustrates how these priorities are assigned to the VBR fields. CBR_TUN = 0, DBL_SLOT = 0 VBR VCC_Index (PRI=VBR_OFFSET+0) CBR_TUN = 0, DBL_SLOT = 1 VBR VCC_Index (PRI=VBR_OFFSET+0) VBR VCC_Index (PRI=VBR_OFFSET+2) Mindspeed Technologies ™ CN8237 Figure 6-4. The SAR can assign VBR VCC_Index (PRI=VBR_OFFSET+1) VBR VCC_Index (PRI=VBR_OFFSET+1) VBR VCC_Index ...

Page 167

... Cell Scheduler Functional Description 6-5. VCC_Index SLOT_DEPTH = 000 (PRI=VBR_OFFSET+0) VCC_Index SLOT_DEPTH = 001 (PRI=VBR_OFFSET+2) VCC_Index SLOT_DEPTH = 010 (PRI=VBR_OFFSET+4) VCC_Index SLOT_DEPTH = 111 (1) Mindspeed Technologies ™ 6.0 Traffic Management CBR_TUN = 0 VBR/ABR VBR/ABR VCC_Index (PRI=VBR_OFFSET+1) VBR/ABR VBR/ABR VCC_Index (PRI=VBR_OFFSET+3) VBR/ABR VBR/ABR VCC_Index ...

Page 168

... Priority 3) VBR2 (VBR/ABR Priority 2) ABR (VBR/ABR Priority 1) UBR2 UBR3 VBR_OFFSET + (# of VBR / ABR priorities) < 15 Mindspeed Technologies ™ CN8237 Service/Application Voice — AAL1 on AAL0 VCCs (Scheduling Priorities 8 thru 15 are not used in the scheme.) Signalling, ILMI, PNNI Traffic Tunnel Through Public ATM Network Tunnel Through Private ATM Network rt-VBR — ...

Page 169

... To achieve the maximum rate, the user assigns one VCC to every cell slot in the Schedule table. This prevents any other VCC from being scheduled since this channel uses all of the available slots. 28237-DSH-001-C 6.2 xBR Cell Scheduler Functional Description clock frequency (SYSCLK or SCHREF) R max Mindspeed Technologies ™ 6.0 Traffic Management is the maximum rate in max 6-13 ...

Page 170

... Schedule table (R ) max x(TBL_SIZE –1) / TBL_SIZE, R max max TBL_SIZE,... ..., R max displays an example of a Schedule table with slots assigned to various SCHEDULE TABLE Mindspeed Technologies CN8237 x(TBL_SIZE – 2)/ max / TBL_SIZE / TBL_SIZE. max 09 VCC_INDEX = SCHEDULE SLOT ™ 28237-DSH-001-C 8237_062 ...

Page 171

... Cell Scheduler Functional Description illustrates this interface. Segmentation Coprocessor PHY Interface Schedule Table Mindspeed Technologies ™ 6.0 Traffic Management Cells are added at CBR rate TX_FIFO (1-9 Cells) Cells are removed at (Line rate — Line overhead) 8237_063 Figure 6-9 illustrates an example ...

Page 172

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management Figure 6-10, where the beginning and end of a Schedule Table CDV max = 1 / (CBR rate in cells / sec) + TX_FIFO_LEN / (line rate in cells/sec) 6.2.2.4). TX_FIFO_LEN > (worst case PCI latency) / (line rate in cells / sec) Mindspeed Technologies ™ CN8237 8237_065 28237-DSH-001-C ...

Page 173

... The host must configure the CBR VCC rate slightly higher than the actual rate of the data source. Skipping cell transmission slots then compensates for the rate differential. 28237-DSH-001-C 6.2 xBR Cell Scheduler Functional Description Mindspeed Technologies ™ 6.0 Traffic Management 6-17 ...

Page 174

... TM 4.1 does not employ single leaky bucket. VBR.1 Double leaky bucket. VBR.2 /VBR.3 TM 4.1 defines two conformance standards for CLP(0+1). 6-14, for the definition of a bucket table entry.) There is complete flexibility I1 = PCR CDVT SCR SCR BT PCR CDVT Mindspeed Technologies ™ CN8237 Comments 28237-DSH-001-C ...

Page 175

... Another method of limiting the bandwidth that a UBR priority consumes is described in 28237-DSH-001-C 6.2 xBR Cell Scheduler Functional Description ((# VBR VCCs at same-or-higher priority)+TX_FIFO_LEN) / (line rate in cells/sec). Section 6.2.8. Mindspeed Technologies ™ 6.0 Traffic Management (TBL_SIZE – n), / max (TBL_SIZE –1). / ...

Page 176

... If both non-tunnel and tunnel scheduling priorities exist, the host must assign the highest priority level(s) to CBR tunnel(s). 6-20 ATM OC-12 ServiceSAR Plus with xBR Traffic Management The format of a CBR tunnel schedule table slot is not backward- compatible with the CBR tunnel format used in the Bt8233 SAR. Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 177

... VBR/ABR priorities is 12. CBR_TUN = 1, SLOT_DEPTH = 110. Highest VBR/ABR Scheduling priority is 15 (that is, PRI=15). Thus, VBR_OFFSET = 3. 28237-DSH-001-C 6.2 xBR Cell Scheduler Functional Description Mindspeed Technologies ™ 6.0 Traffic Management 6-21 ...

Page 178

... MCR on GFR channels and other rate-guaranteed services. 6-22 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Example of Multi-Service Tunnels Tunnel B Tunnel C rt-VBR rt-VBR nrt-VBR nrt-VBR ABR ABR ABR UBR UBR UBR Mindspeed Technologies ™ CN8237 Tunnel D rt-VBR nrt-VBR ABR UBR 8237_066 28237-DSH-001-C ...

Page 179

... QPCR_INT2 are used, and so on. 28237-DSH-001-C 6.2 xBR Cell Scheduler Functional Description Set NONZERO bits to 1. Set MCR_EXP fields to decimal value of 31 (that is, all-1s). Set MCR_MAN fields to decimal value of 511 (that is, all-1s). Mindspeed Technologies ™ 6.0 Traffic Management Table 6-18), each containing MCR Section 6 ...

Page 180

... Figure 6-12. ABR Service Category Feedback Control Source Variable Rate Shaping BW_RM (Backward_RM) 6-24 ATM OC-12 ServiceSAR Plus with xBR Traffic Management illustrates this basic concept. FW_RM (ForWard_RM) Switch Congestion Algorithms ATM Network ( 1 Switches) Mindspeed Technologies ™ CN8237 Destination TA_RM (TurnAround_RM) Internal Congestion Backpressure 8237_067 28237-DSH-001-C ...

Page 181

... SEG VCC Table Entry SCH_STATE Rate Cell Type Decision Decision Cell Segmentation Scheduler Coprocessor SAR Reassembly Coprocessor RSM VCC Table Entry Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager UNI ATM Network + Destination ABR Cell Stream BACKWARD_RM 8237_068 6-25 ...

Page 182

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management Figure 6-14. (Backward RM Cell Formatting) Seg VCC Table Entry Segmentation Coprocessor SCH_STATE Turnaround Reassembly Information Coprocessor (Forward RM Cell Processing) Mindspeed Technologies ™ CN8237 Congestion Host Backpressure 8237_069 28237-DSH-001-C ...

Page 183

... Exponent table is indexed by the Explicit Rate exponent. This mapping function normalizes the ER field rate to the CI/NI state-based rate decision. Once normalized, a rate can be chosen based on the minimum of the two rates. 28237-DSH-001-C Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager ...

Page 184

... Furthermore, since immature specification, the rules for cell interleaving of in-rate cell streams may be modified slightly. 6-28 ATM OC-12 ServiceSAR Plus with xBR Traffic Management shows the desired result of the specification. First, the Source Nrm Data Cells FW_RM Mindspeed Technologies ™ CN8237 BW_RM 8237_070 28237-DSH-001-C ...

Page 185

... VCC has no user data to segment. Data Cell Forward RM Backward RM None Cell Type Action ABR Cell Flow Decision Control Table Manager Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager shows a block diagram of the ABR-ER Cell Stream 8237_071 6-29 ...

Page 186

... ATM OC-12 ServiceSAR Plus with xBR Traffic Management Name TRM_EXP Time since last forward RM transmitted TA_PND TA_PND bit set in VCC table entry TA_XMIT TA_XMIT bit set in VCC table entry RUN RUN bit set in VCC table entry Mindspeed Technologies ™ CN8237 Table 6-5 shows the four Description TRM 28237-DSH-001-C ...

Page 187

... Nrm = 32 28237-DSH-001-C CELL_INDEX(++) ABR CELL DECISION BLOCK 7-BRM 6-BRM 15-FRM 14-FRM ABR Cell Type Decision Vector (ACDV) [TRM_EXP, TA_PND, TA_XMIT, RUN] = 0001b Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager 1-DATA 0-NONE 9-FRM 8-FRM 8237_072 6-31 ...

Page 188

... Forward RM cell. The decision process is unique for each event type. NOTE: 6-32 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Both of these event types may occur in one cell slot. In this case, the CN8237 makes both decisions before updating ACR. Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 189

... Backward RM flow control. SEG VCC Table Entry SCH_STATE (RATE_INDEX) Rate Decision Cell Segmentation Scheduler Coprocessor SAR (CI, NI, and ER Fields) Reassembly Coprocessor Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager UNI ATM Network + Destination ABR Cell Stream BACKWARD_RM 8237_073 6-33 ...

Page 190

... ABR Exponent table. Again, the system designer pre-calculates this mapping function to eliminate real-time floating point math. 6-34 ATM OC-12 ServiceSAR Plus with xBR Traffic Management illustrates the RR Rate_INDEX candidate selection. RR INDEX CONNECTION STATE (RATE_INDEX) CANDIDATE Mindspeed Technologies ™ CN8237 ACR x RDF (COMPLIANT RELATIVE RATES) 8237_074 28237-DSH-001-C ...

Page 191

... ER RATE_INDEX candidate selection. ER INDEX CONNECTION STATE (RATE_INDEX) CANDIDATE MCR. The winning candidate then replaces the current provides a block diagram of this process. The reassembly MCR. The min() function is applied to select a winning Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager 8237_075 6-35 ...

Page 192

... VCC, ER, CI, NI CI, NI Rate Decision Piece-Wise Vector Table Linear Mapping Traversal Function RR RATE_INDEX Update Min( ) RATE_INDEX -> NEW RATE Rate Decision Block I and L parameters Dynamic Scheduler Mindspeed Technologies ™ CN8237 ABR Traffic Manager ER Exponent Table ER RATE_INDEX TM4.0 ABR Rate-Shaped Traffic 8237_076 28237-DSH-001-C ...

Page 193

... Either this is the first notification or the last notification was triggered from NCR_LO. (1) For the destination change notification, this can be either ACR or ER depending on ACR_NOT_ER value. Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager PCR. This happens Section 4 ...

Page 194

... The maximum index into the rate table has an offset of 4096 words to the ER_SHIFT_B base address. Multiple ER_HC_RATE tables might be used. 6-38 ATM OC-12 ServiceSAR Plus with xBR Traffic Management 2^^(9 >> HC_SHIFT HC_EXP × HC_MANT/512) Mindspeed Technologies ™ CN8237 Figure 6-22). Each entry 28237-DSH-001-C ...

Page 195

... Entry 1 Entry 29 Entry 31 Entry 1 0 Entry 29 Entry 31 0 Rate Entry 1 Mantissa Shift HC_Index Rate Entry n-2 Rate Entry n Mindspeed Technologies ™ 6.0 Traffic Management 6.3 ABR Flow Control Manager ER_SHIFT Entry 0 Table 0 Entry 28 Entry 30 ER_SHIFT Entry 0 Table 63 Entry 28 Entry 30 ER_HC_RATE ...

Page 196

... ACR_TO. If the trigger point for the timeout has been reached, the CN8237 generates a new Forward RM cell with the ACR_INDEX value as the assigned new explicit rate. 6-40 ATM OC-12 ServiceSAR Plus with xBR Traffic Management Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 197

... GFC is used to coordinate access to that bandwidth when temporary conflicts occur. 28237-DSH-001 (maximum scheduled rate) = sysclk / SLOT_PER generated rate = R / (OOR_INT + 1) / (VCC_MAX / Mindspeed Technologies ™ 6.0 Traffic Management 6.4 GFC Flow Control Manager 6-41 ...

Page 198

... The user must control the transmitted GFC field via the HEADER_MOD and GFC_DATA fields in the buffer descriptor entries. For GFC-controlled channels, GFC_DATA = 0101; and for non-GFC-controlled-channels, GFC_DATA = 0001. 6-42 ATM OC-12 ServiceSAR Plus with xBR Traffic Management 6.4.2.1), a received HALT indication causes the segmentation Mindspeed Technologies ™ CN8237 28237-DSH-001-C ...

Page 199

... Set the GFCn bit(s) in the SCH_PRI register to enable the appropriate priority queue(s) for GFC-controlled operation. Set the framer chip to generate unassigned cells with GFC field in cell headers set to the value of 0001. (Reserved for 1 VBR/ABR pointer) (Reserved for 2 16-bit VBR/ABR pointers) Mindspeed Technologies ™ 6.0 Traffic Management Table 6-6. 6-43 ...

Page 200

... If three priorities are to be assigned to the tunnel, assigns the priorities by level to PRI3 (highest), PRI2 and PRI1 (lowest), making PRI0 the same as PRI1. TUN_PRI0_OFFSET can be used to set PRI0 = PRI1, as needed. 6-44 ATM OC-12 ServiceSAR Plus with xBR Traffic Management CBR_VCC_INDEX (15 bits PRI2 Description Mindspeed Technologies ™ CN8237 Table 6- Table 6-8. The Table 6- ...