XC4028EX-4BG352I Xilinx Inc, XC4028EX-4BG352I Datasheet - Page 12

• Manufacturer Part Number: XC4028EX-4BG352I
• Description: FPGA XC4000E Family 28K Gates 2432 Cells 0.35um Technology 5V 352-Pin BGA
• Manufacturer: Xilinx Inc

Specifications of XC4028EX-4BG352I

• Package: 352BGA
• Family Name: XC4000E
• Device Logic Gates: 28000
• Device Logic Units: 2432
• Device System Gates: 50000
• Number Of Registers: 2560
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 256
• Ram Bits: 32768
• Re-programmability Support: Yes

XC4000E and XC4000X Series Field Programmable Gate Arrays
Figure 8
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Table
Figure 9
figured as 16x2 and 32x1 level-sensitive, single-port RAM.
Initializing RAM at Configuration
Both RAM and ROM implementations of the XC4000
Series devices are initialized during configuration. The ini-
tial contents are defined via an INIT attribute or property
6-16
Figure 7: 16x1 Edge-Triggered Dual-Port RAM
Figure 8: Level-Sensitive RAM Write Timing
7.
and
shows the write timing for level-sensitive, sin-
G 1 • • • G 4
C 1 • • • C 4
F 1 • • • F 4
(CLOCK)
WRITE ENABLE
Figure 10
ADDRESS
K
DATA IN
4
show block diagrams of a CLB con-
WE
Product Obsolete or Under Obsolescence
4
4
D 1
T
AS
D 0
LATCH
ENABLE
LATCH
ENABLE
4
4
EC
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not defined, all RAM contents
are initialized to all zeros, by default.
RAM initialization occurs only during configuration. The
RAM content is not affected by Global Set/Reset.
Table 7: Single-Port Level-Sensitive RAM Signals
D
A[3:0]
WE
O
DECODER
DECODER
T
WC
WRITE
WRITE
1 of 16
1 of 16
RAM Signal
T
WP
WRITE PULSE
WRITE PULSE
REQUIRED
16-LATCH
16-LATCH
T
ARRAY
ARRAY
DS
D0 or D1
F1-F4 or G1-G4
WE
F’ or G’
D
D
IN
IN
CLB Pin
ADDRESS
ADDRESS
READ
READ
T
AH
T
May 14, 1999 (Version 1.6)
MUX
MUX
DH
Data In
Address
Write Enable
Data Out
X6462
X6748
Function
G'
F'
R