XC4028EX-4BG352I Xilinx Inc, XC4028EX-4BG352I Datasheet - Page 51

• Manufacturer Part Number: XC4028EX-4BG352I
• Description: FPGA XC4000E Family 28K Gates 2432 Cells 0.35um Technology 5V 352-Pin BGA
• Manufacturer: Xilinx Inc

Specifications of XC4028EX-4BG352I

• Package: 352BGA
• Family Name: XC4000E
• Device Logic Gates: 28000
• Device Logic Units: 2432
• Device System Gates: 50000
• Number Of Registers: 2560
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 256
• Ram Bits: 32768
• Re-programmability Support: Yes

Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfer-
ing with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function genera-
tors used as RAMs.
Note that in XC4000 Series devices, configuration data is
not inverted with respect to configuration as it is in XC2000
and XC3000 families.
XC4000 Series Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, place the READ-
May 14, 1999 (Version 1.6)
Figure 48: Start-up Logic
CLEAR MEMORY
LENGTH COUNT
STARTUP
STARTUP.CLK
USER NET
CCLK
FULL
Q3
Q2
R
*
*
*
S
K
Q
Product Obsolete or Under Obsolescence
Q0
0
1
M
*
1
0
*
1
0
0
1
CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"
Q1/Q4
DONE
IN
XC4000E and XC4000X Series Field Programmable Gate Arrays
D
K
GSR ENABLE
GSR INVERT
STARTUP.GSR
STARTUP.GTS
GTS INVERT
GTS ENABLE
Q
Q1
D
K
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
Q
Q2
1
0
M
*
BACK library symbol and attach the appropriate pad sym-
bols, as shown in
After Readback has been initiated by a High level on
RDBK.TRIG after configuration, the RDBK.RIP (Read In
Progress) output goes High on the next rising edge of
RDBK.CLK. Subsequent rising edges of this clock shift out
Readback data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
D
Q
K
S
R
Q
Q3
GLOBAL SET/RESET OF
ALL CLB AND IOB FLIP-FLOP
IOBs OPERATIONAL PER CONFIGURATION
GLOBAL 3-STATE OF ALL IOBs
Figure
D
K
Q
49.
Q4
1
0
X1528
" FINISHED "
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
DONE
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