XC4028EX-4BG352I Xilinx Inc, XC4028EX-4BG352I Datasheet - Page 59

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XC4028EX-4BG352I

Manufacturer Part Number
XC4028EX-4BG352I
Description
FPGA XC4000E Family 28K Gates 2432 Cells 0.35um Technology 5V 352-Pin BGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC4028EX-4BG352I

Package
352BGA
Family Name
XC4000E
Device Logic Gates
28000
Device Logic Units
2432
Device System Gates
50000
Number Of Registers
2560
Typical Operating Supply Voltage
5 V
Maximum Number Of User I/os
256
Ram Bits
32768
Re-programmability Support
Yes

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Figure 55: Master Parallel Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
(output)
(output)
(output)
(output)
A0-A17
D0-D7
DOUT
RCLK
CCLK
RCLK
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
Low until Vcc is valid.
R
Delay to Address valid
Data setup time
Data hold time
Product Obsolete or Under Obsolescence
Description
XC4000E and XC4000X Series Field Programmable Gate Arrays
Address for Byte n
1
2
3
Symbol
7 CCLKs
T
T
T
DRC
RCD
RAC
2 T
Byte
DRC
Min
60
0
0
Byte n - 1
D6
Address for Byte n + 1
1 T
3 T
CCLK
RAC
Max
RCD
200
D7
Units
ns
ns
ns
X6078
6-63
6

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