MT9092AP Zarlink, MT9092AP Datasheet
MT9092AP
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MT9092AP Summary of contents
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... ISO -CMOS ST-BUS Digital Telephone with HDLC (HPhone-II) MT9092APR MT9092AP MT9092APR1 MT9092AP1 Description The MT9092 HPhone- fully featured integrated digital telephone circuit which includes an HDLC data formatter. Voice band signals are converted to digital PCM and vice versa by a switched capacitor Filter/Codec. ...
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... F0i 11 35 IRQ PIN PLCC Figure 2 - Pin Connections Description /2) volts is available at this pin for biasing external amplifiers SSA . SSA for normal operation Zarlink Semiconductor Inc. Data Sheet SPKR+ SPKR- HSPKR+ HSPKR- VDD BP S12 S11 S10 S9 S8 /2)-1.5] volts. Used internally. DD ...
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... NOTES: Intel and MCS-51 are registered trademarks of Intel Corporation, Santa Clara, CA, USA. MT9092 Description This input signal is used to select the device for microport data for normal operation. SS Handsfree microphone amplifier inverting input Handsfree microphone amplifier non- 3 Zarlink Semiconductor Inc. Data Sheet ...
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... The Filter/CODEC block implements conversion of the analog 3.3kHz speech signals to/from the digital domain compatible with 64 kb/s PCM B-Channels. Selection of companding curves and digital code assignment are register programmable. These are CCITT G.711 A-law or µ-Law, with true-sign/ Alternate Digit Inversion or true- MT9092 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Ref pins are situated on adjacent pins. -STG (address 0Bh -TxFG 0 2 -STG control bits located in the FCODEC Gain Control Register Zarlink Semiconductor Inc. Data Sheet is also brought to an external pin so that it and RxFG -RxFG control bits respectively for Bias Bias Ref ...
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... Transmit Filter Gain 0 to +7dB (1 dB steps) µ-Law 6.1dB Α-Law 15.4dB ANALOG DOMAIN Figure 3 - Audio Gain Partitioning 6 Zarlink Semiconductor Inc. Data Sheet Handset Receiver (150Ω) µ-Law –6 Α-Law –3.7 dB HSPKR+ Receiver 75 Driver HSPKR– ...
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... B0 - B5). The power up reset program sets the default values such that the receive gain is set to -72.0 dB, the transmit audio gain is set to 0.0 dB and the transmit DTMF gain is set to -3.0 dB (equivalent to a DTMF output level of -4 dBm0 into the network). MT9092 7 Zarlink Semiconductor Inc. Data Sheet ...
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... COEFF = 0.128 x Frequency (in Hz) Actual COEF (Hz) Frequency 697 59h 695.3 770 63h 773.4 852 6Dh 851.6 941 79h 945.3 1209 9Bh 1210.9 1336 ABh 1335.9 1477 BDh 1476.6 1633 D1h 1632.8 Table 1 - DTMF Frequencies 8 Zarlink Semiconductor Inc. Data Sheet % Deviation -.20% +.40% -.05% +.46% +.20% .00% -.03% -.01% ...
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... The DSP can be made to send quiet code to the decoder and receive filter path by setting the RxMUTE bit high. Likewise, the DSP will send quiet code in the transmit (DSTo) path when the TxMUTE bit is high. Both of these MT9092 COEFF = 8000/Frequency (Hz) Tone duration (warble frequency in Hz) = 500/COEFF 9 Zarlink Semiconductor Inc. Data Sheet ...
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... A packet does not need to contain an information field to be valid. The HDLC does not distinguish between the control field and the information field. MT9092 DATA FIELD FCS FLAG n Bytes Two One (nŠ2) Bytes Byte Figure 4 - Frame Format 10 Zarlink Semiconductor Inc. Data Sheet ...
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... An idle channel occurs when at least fifteen contiguous 1s are transmitted or received. In both cases the transmitter will exit the wait state when data is loaded into the transmit FIFO. MT9092 5 +1 produces the 16-bit FCS. In the transmitter the FCS is calculated on all bits 11 Zarlink Semiconductor Inc. Data Sheet ...
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... HDLC Status Register (address 04h) should be read. Due to the asynchronous nature of the interrupts an interrupt occurring during a read of the Interrupt Status register will be held until the read cycle is over, unless interrupt which is already valid. MT9092 12 Zarlink Semiconductor Inc. Data Sheet ...
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... Idle Channel When the receiver detects at least 15 contiguous ones it declares an idle channel condition exists and sets the IdleChan bit in the HDLC status register high (address 04h). This bit remains set until the received condition changes. MT9092 13 Zarlink Semiconductor Inc. Data Sheet ...
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... The receiver will be re-enabled when the next flag is detected but will overflow again if the Rx FIFO level has not been reduced to less than full. If two 'first byte' (RxBS1 and RxBS2) conditions are observed in the FIFO without an intervening 'last byte' then an overflow occurred for the first packet. MT9092 14 Zarlink Semiconductor Inc. Data Sheet ...
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... Interrupt registers may still be read and control registers written while the receiver is disabled. Note that the receiver requires the reception of a flag before processing a packet, thus if the receiver is enabled in the middle of an incoming packet it will ignore that packet and wait for the next complete one. MT9092 15 Zarlink Semiconductor Inc. Data Sheet Note that this register bit ...
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... Tx FIFO Status TxFULL 5 OR MORE BYTES (15 if Fltx set LESS BYTES (14 if Fltx set) TxEMPTY Rx FIFO Status RxEMPTY 14 OR LESS BYTES (4 if Flrx set MORE BYTES (5 if Flrx set) RxOVERFLOW EXISTS Table 2 - HDLC Status Bits 16 Zarlink Semiconductor Inc. Data Sheet EN must 0 ...
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... Transducer Control Register (address 0Eh). The nominal gain for this amplifier is 0.2 dB. C-Channel Access to the internal control and status registers of Zarlink basic rate, layer 1, transceivers is through the ST-BUS Control Channel (C-Channel), since direct microport access is not usually provided, except in the case of the SNIC (MT8930) ...
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... A serial link is required for the transport of data between the HPhone-II and the external digital transmission device. The HPhone-II utilizes the ST-BUS architecture defined by Zarlink Semiconductor. Refer to Zarlink Application Note MSAN-126. The HPhone-II ST-BUS consists of output and input serial data streams, DSTo and DSTi respectively, a synchronous clock signal C4i, and a framing pulse F0i ...
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... EN - C-Channel 1 Channel 1 conveys the control/status information for Zarlink’s layer 1 transceiver. The full 64 kb/s bandwidth is available and is assigned according to which transceiver is being used. Consult the data sheet for the selected transceiver for its bit definitions and order of bit transfer. When this bit is high register data is transmitted on DSTo ...
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... Register 2 (address 0Bh). MT9092 125 µs CHANNEL 2 CHANNEL 3 CHANNELS B1-channel B2-channel Not Used Channels Figure 7 - ST-BUS Channel Assignment -NCTG 0 20 Zarlink Semiconductor Inc. Data Sheet EN and Ch EN) are used and Ch EN are enabled, default reside in the FCODEC Gain Control 1 EN and ...
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... Setting this bit causes data on DSTi to be looped back to DSTo directly at the pins. The appropriate channel enables Ch EN -Ch 0 LBoi Setting this bit causes data on DSTo to be looped back to DSTi directly at the pins. MT9092 must also be set Zarlink Semiconductor Inc. Data Sheet , for operation ...
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... TONE COEFFICIENT REGISTER 2 25 RESERVED 26 TONE RINGER WARBLE RATE REGISTER 27-3F RESERVED MT9092 WRITE NOT USED NOT USED 22 Zarlink Semiconductor Inc. Data Sheet READ VERIFY VERIFY HDLC RECEIVE FIFO VERIFY HDLC STATUS REGISTER VERIFY VERIFY HDLC INTERRUPT STATUS REGISTER RESERVED RESERVED ...
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... ADDRESS = 00h WRITE/READ VERIFY Adr13 Adr12 Adr11 Adr10 A1EN ADDRESS = 01h WRITE/READ VERIFY Adr23 Adr22 Adr21 Adr20 A2EN Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 0 Power Reset Value 0000 0000 0 ADDRESS = 02h WRITE/READ Power Reset Value Not Applicable 0 ...
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... No CRC bytes are sent or monitored nor are flags, aborts or Go-aheads. No address recognition is monitored. The receiver or transmitter must be enabled through Control Register 1 as well as setting CH MT9092 ADDRESS = 03h WRITE/READ VERIFY Mark EOP FA Trans Idle Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 - EN. 0 ...
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... OR MORE BYTES (15 if Fltx set LESS BYTES (14 if Fltx set) TxEMPTY Rx FIFO Status RxEMPTY 14 OR LESS BYTES (4 if Flrx set MORE BYTES (5 if Flrx set) RxOVERFLOW EXISTS 25 Zarlink Semiconductor Inc. Data Sheet ADDRESS = 04h READ Power Reset Value 00XX 1000 1 0 ...
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... Note: Bits marked "-" are reserved bits and should be written with logic "0". MT9092 ADDRESS = 05h WRITE/READ VERIFY Seven Flrx Fltx Rxfrst Txfrst ADDRESS = 06h WRITE/READ VERIFY FA/Tx EOPR TxFL RxFf Under Ovfl Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 0 Power Reset Value Rx 0000 0000 0 ...
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... Transmit Gain RxFG RxFG 1 0 Setting (dB (default TxFG 27 Zarlink Semiconductor Inc. Data Sheet ADDRESS = 07h READ Power Reset Value Rx 0000 0000 Ovfl 0 ADDRESS = 08h and 09h are RESERVED ADDRESS = 0Ah WRITE/READ VERIFY Power Reset Value X000 X000 TxFG 0 0 TxFG TxFG TxFG ...
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... When low, the sidetone path is disabled. 2-0 ± muxed into the transmit path. When low, the handset microphone (pins 28 Zarlink Semiconductor Inc. Data Sheet ADDRESS = 0Bh WRITE/READ VERIFY Power Reset Value 0X00 X000 STG 0 0 STG STG ...
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... Zarlink Semiconductor Inc. Data Sheet ADDRESS = 0Fh WRITE/READ VERIFY Power Reset Value NCT 0000 0000 µ ADDRESS 10h is RESERVED ADDRESS = 11h WRITE Power Reset Value XXX0 1010 ADDRESS = 12h WRITE/READ VERIFY Power Reset Value 0000 0000 ADDRESS = 13h WRITE/READ VERIFY Power Reset Value ...
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... and Zarlink Semiconductor Inc. Data Sheet ADDRESS = 14h WRITE/READ Power Reset Value Write = 1111 1111 D 0 Read = Not Applicable 0 ADDRESS = 15h WRITE/READ VERIFY Power Reset Value XX0X 0000 are enabled, data defaults to channel and Ch 2 ADDRESS = 16h WRITE/READ VERIFY Power Reset Value ...
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... Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 B0 0 Gain Setting (dB) -25.5 -27.0 -28.5 -30.0 -31.5 -33.0 -34.5 -36.0 -37.5 -39.0 -40.5 -42.0 -43.5 -45.0 -46.5 -48.0 -49.5 -51 ...
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... Reserved 1 1 Reserved Zarlink Semiconductor Inc. Data Sheet ADDRESS = 1Eh WRITE/READ VERIFY Power Reset Value - DRESET 0000 0000 1 0 ADDRESS = 20h WRITE/READ VERIFY Power Reset Value B0 XX11 0000 0 ADDRESS = 21h WRITE/READ VERIFY Power Reset Value B0 XX10 1110 0 ADDRESS 22h is RESERVED ...
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... Hz 31.4 Hz non-linear ADDRESS = 24h WRITE/READ VERIFY 1992.2 Hz 7.8 Hz 7.8 Hz 0dB ADDRESS = 26h WRITE/READ VERIFY 500 Hz 2.0 Hz non-linear 33 Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 0000 Power Reset Value 0000 0000 ADDRESS 25h is RESERVED Power Reset Value 0000 0000 ...
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... In this case the dynamic range of the MT9092 is reduced by half. In both figures the output drivers are connected in a fully differential manner. The MT9092 is a member of the Zarlink family of digital terminal equipment components. There are two transmisssion devices which connect directly with the MT9092 to complete an application; the MT8930 (SNIC) and the MT8971/72 (DSIC/DNIC). An ISDN 4-wire " ...
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... Electret + Microphone R 0.1µF VBias MT9092 LCD 35 Zarlink Semiconductor Inc. Data Sheet 330Ω + VBias +5V + – 1µF + Electret Microphone + 40Ω nom. 32Ω min. 75Ω 150Ω 75Ω +5V .1µF 1000pF 1000pF 1000pF caps are optional LCD Note: Single-ended configurations reduce dynamic range by a factor of two. 10µ ...
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... DSTi with Telephone HDLC DSTi DSTo Controller Controller AD0-7 IRQ IRQ CS SCLK (ALE) (RD) (WR) AS (ALE) AD0-7 8051 INTEL IRQ 36 Zarlink Semiconductor Inc. Data Sheet HSPKR+ HSPKR- Handset M+ MT9092 M- Digital MIC+ with Microphone MIC- HDLC SPKR+ Speaker SPKR- DATA1 E R/W (RD) (WR) MCS- ...
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... Address 15h bits (as required) 37 Zarlink Semiconductor Inc. Data Sheet HSPKR+ HSPKR- Handset M+ MT9092 HPhone-∏ M- Digital Telephone with MIC+ HDLC Microphone ...
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... Address DATA 15h bits (as required) 1Eh 00h 1Dh 70h (or as required) 20h 30h (or as required) 23h as required 24h as required 26h as required 1Eh 61h 0Eh 82h 1Eh 61 (on) 69 (off) 61 (on) 69 (off) etc... 38 Zarlink Semiconductor Inc. Data Sheet ...
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... NCTG2-1 (as required) 0Eh 02h 9Bh (assuming a concurrent handset call) 01h (assuming all other bits are µ-Law 0Fh 1Eh 71h (on) 31h (off) 71h (on) etc... 39 Zarlink Semiconductor Inc. Data Sheet ...
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... CLK Sym. Min. Typ. Max. I DDC1 I 1.5 DDF1 I 1.0 DDF2 I 1.5 DDF3 I 1.5 DDF4 I 1.5 DDF5 I 1.0 DDF6 I 8.0 DDFT 40 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 -0 ±20 mA °C -65 +150 750 mW ±2.0 KV ±100 mA Units Test Conditions V V Noise margin = 400mV ...
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... Voltages are with respect to ground (V Sym. Min. Typ. Max. V 4.8 --- --- OH V --- --- 0.2 OL --- --- 1200 --- --- 7200 62 62 Zarlink Semiconductor Inc. Data Sheet ) unless otherwise stated. SS Units Test Conditions Max. Load = 10kΩ µ 2.4V DSTo, WD, OH DATA1, DATA2, IRQ 0.4V DSTo, WD, OL DATA1, ...
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... D 360 AX D 750 DX 380 130 750 PSSR 37 PSSR1 40 PSSR2 35 PSSR3 40 42 Zarlink Semiconductor Inc. Data Sheet for A-Law, at the CODEC. (V rms Ref Units Test Conditions µ-Law Vp-p Vp-p A-Law Both at CODEC dB MICA/u=0* dB MICA/u=1* MIC± or M± to PCM 1020Hz dB ...
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... D 240 AR D 750 DR 380 130 750 Zarlink Semiconductor Inc. Data Sheet for A-Law, at the CODEC. (V rms Ref Units Test Conditions µ-Law Vp-p Vp-p A-Law dB PCM to SPKR± dB PCM to HSPKR±, RxA/u=0* dB PCM to HSPKR±, RxA/u=1* 1020Hz dB PCM to SPKR± ...
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... AS1 G -13.1 -12.6 -12.1 AS2 G -0.3 +0 -0.3 +0 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions dB SIDEA/u, MICA/u, RxA/u all 0 dB SIDEA/u, MICA/u, RxA/u all 1 M± inputs to HSPKR± outputs 1000Hz dB SIDEA/u=0 dB SIDEA/u=1 from nominal relative measurements w.r.t. G & G ...
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... S 0.5 D ‡ Sym. Min. Typ. Max. V 2. Zarlink Semiconductor Inc. Data Sheet Test Conditions NCTG0=0, NCTG1=0 NCTG0=1, NCTG1=0 NCTG0=0, NCTG1=1 NCTG0=1, NCTG1=1 load > 34 ohms across SPKR± Test Conditions ohms across HSPKR± pF each pin: HSPKR+ HSPKR- % 300 ohms load across HSPKR± ...
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... C4H t 121 122 123 C4L F0iS t 50 F0iH t 150 F0iW t 100 125 DSToD t 30 DSTiS t 50 DSTiH 1 bit cell t C4P t DSToD t DSTiS t t F0iH T t F0iW Figure 12 -ST-BUS Timing Diagram 46 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions = C4H C4L t DSTiH ...
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... Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. DATA 1 0 RECEIVE SCLK DATA 1 or DATA 2 TRANSMIT MT9092 ‡ Sym. Min. Typ 333 Figure 13 - Serial Microport Timing Diagram 47 Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...