XC4028EX-3HQ240I Xilinx Inc, XC4028EX-3HQ240I Datasheet - Page 37

• Manufacturer Part Number: XC4028EX-3HQ240I
• Description: FPGA XC4000E Family 28K Gates 2432 Cells 0.35um Technology 5V 240-Pin HSPQFP EP
• Manufacturer: Xilinx Inc

Specifications of XC4028EX-3HQ240I

• Package: 240HSPQFP EP
• Family Name: XC4000E
• Device Logic Gates: 28000
• Device Logic Units: 2432
• Device System Gates: 50000
• Number Of Registers: 2560
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 193
• Ram Bits: 32768
• Re-programmability Support: Yes

Table 16: Pin Descriptions (Continued)
May 14, 1999 (Version 1.6)
(XC4000XLA
XC4000XV
Pin Name
(XC4000E
(XC4000E
(XC4000X
TDI, TCK,
PGCK1 -
SGCK1 -
FCLK1 -
PGCK4
SGCK4
GCK1 -
FCLK4
GCK8
TMS
HDC
only)
only)
only)
only)
LDC
INIT
and
R
Config.
During
Pull-up
Pull-up
Pull-up
Pull-up
Weak
Weak
Weak
Weak
I/O
I/O
O
O
I
Product Obsolete or Under Obsolescence
Config.
(JTAG)
I or I/O
I or I/O
I or I/O
I or I/O
After
or I
I/O
I/O
I/O
I/O
I/O
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-
ited once configuration is completed, and these pins become user-programmable I/O.
The pins can be used automatically or user-constrained. To use them, use "LOC=" or
place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-
put or output buffers must still be used.
High During Configuration (HDC) is driven High until the I/O go active. It is available as
a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
control output indicating that configuration is not yet completed. After configuration,
LDC is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 k - 10 k external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active-Low input, it can be used
to hold the FPGA in the internal WAIT state before the start of configuration. Master
mode devices stay in a WAIT state an additional 30 to 300 s after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin.
Four Primary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-
grammable I/O.
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol
connected directly to the input of a BUFGP symbol is automatically placed on one of
these pins.
Four Secondary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff-
ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto-
matically placed on one of these pins.
Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo-
bal Early buffer. Each pair of global buffers can also be driven from internal logic, but
must share an input signal. If not used to drive a global buffer, any of these pins is a
user-programmable I/O.
Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol
is automatically placed on one of these pins.
Four inputs can each drive a Fast Clock (FCLK) buffer which can deliver a clock signal
to any IOB clock input in the octant of the die served by the Fast Clock buffer. Two Fast
Clock buffers serve the two IOB octants on the left side of the die and the other two Fast
Clock buffers serve the two IOB octants on the right side of the die. On each side of the
die, one Fast Clock buffer serves the upper octant and the other serves the lower octant.
If not used to drive a Fast Clock buffer, any of these pins is a user-programmable I/O.
XC4000E and XC4000X Series Field Programmable Gate Arrays
Pin Description
6-41
6