P80C592FFA/00,518 NXP Semiconductors, P80C592FFA/00,518 Datasheet - Page 38
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P80C592FFA/00,518
Manufacturer Part Number
P80C592FFA/00,518
Description
IC 80C51 MCU 8BIT ROMLESS 68PLCC
Manufacturer
NXP Semiconductors
Series
80Cr
Datasheet
1.P80C592FFA00512.pdf
(108 pages)
Specifications of P80C592FFA/00,518
Core Processor
8051
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
68-LCC (J-Lead)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P80C592FFA/00,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
Notes to the description of the SR bits
1. When the Bus Status bit is set HIGH (Bus-OFF), the CAN-controller will set the Reset Request bit HIGH (present).
2. If both the Receive Status and Transmit Status bits are LOW (idle) the CAN-bus is idle.
3. If the CPU tries to write to the Transmit Buffer when the Transmit Buffer Access bit is LOW (locked), the written bytes
4. If Data Overrun = HIGH (overrun) is detected, the currently received message is dropped. A transmitted message,
5. If the command bit Release Receive Buffer is set HIGH (released) by the CPU, the Receive Buffer Status bit is set
1996 Jun 27
8-bit microcontroller with on-chip CAN
It will stay in this state until the CPU sets the Reset Request bit LOW (absent). Once this is completed the
CAN-controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) before setting
the Bus Status bit LOW (Bus-ON), the Error Status bit LOW (ok) and resetting the Error Counters. During Bus-OFF
the output drivers are switched off (floating); external transceiver circuits should output a recessive level in this case.
will not be accepted and will be lost without this being signalled. The Transmission Complete Status bit is set LOW
(incomplete) whenever the Transmission Request bit is set HIGH (present). If an Abort Transmission command is
issued, the Transmit Buffer will be released. If the message, which was requested and then aborted, was not
transmitted, the Transmission Complete Status bit will remain LOW.
granted acceptance, is also stored in a Receive Buffer. This occurs because it is not known if the CAN-controller will
lose arbitration and so become a receiver of the message. If no Receive Buffer is available, Data Overrun is
signalled. However, this transmitted and accepted message does neither cause a Receive Interrupt nor set the
Receive Buffer Status bit to HIGH (full). Also, a Data Overrun does not cause the transmission of an Overload Frame
(see Sections 13.6.1 and 13.6.5).
LOW (empty) by IML. When a new message is stored in any of the receive buffers, the Receive Buffer Status bit is
set HIGH (full) again.
38
Product specification
P8xC592