STM32F407VGT6 STMicroelectronics, STM32F407VGT6 Datasheet
STM32F407VGT6
Specifications of STM32F407VGT6
Available stocks
Related parts for STM32F407VGT6
STM32F407VGT6 Summary of contents
Page 1
ARM Cortex-M4 32b MCU+FPU, 210DMIPS 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Features ■ Core: ARM 32-bit Cortex™-M4F CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state ...
Page 2
Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
STM32F405xx, STM32F407xx 2.2.30 2.2.31 2.2.32 2.2.33 2.2.34 2.2.35 2.2.36 2.2.37 2.2.38 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
Contents 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 5.3.19 5.3.20 5.3.21 5.3.22 5.3.23 5.3.24 5.3.25 5.3.26 5.3.27 5.3.28 6 Package characteristics . . . . . . . . . . . . . . . . . . . . ...
Page 5
STM32F405xx, STM32F407xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
List of tables Table 47. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ...
Page 7
STM32F405xx, STM32F407xx List of figures Figure 1. Compatible board design between STM32F2xx and STM32F4xx: LQFP176 . . . . . . . . . . 13 Figure 2. Compatible board design between STM32F1xx/STM32F2xx ...
Page 8
List of figures Figure 45. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
... STM32F405xx, STM32F407xx 1 Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual ...
Page 10
Description 2 Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM Cortex™-M4F 32-bit RISC core operating at a frequency 168 MHz. The Cortex-M4F core features a Floating point unit (FPU) single precision which supports ...
Page 11
Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG Flash memory in Kbytes System SRAM in Kbytes Backup FSMC memory controller No Ethernet General-purpose Advanced- Timers control Basic Random number generator 2 SPI / ...
Page 12
Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued) Peripherals STM32F405RG Operating temperatures Package LQFP64 1. V minimum value of 1 obtained when the device operates in the °C temperature range and PDR_ON is ...
Page 13
STM32F405xx, STM32F407xx 2.1 Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pin- to-pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, ...
Page 14
Description Figure 2. Compatible board design between STM32F1xx/STM32F2xx/ STM32F4xx: LQFP144 Ω default, PDR_ON (pin 143) should be connected Pin 143 is RFU for STM32F2xx. Figure 3. Compatible board design STM32F1xx/STM32F2xx/ STM32F4xx: LQFP100 Ω ...
Page 15
STM32F405xx, STM32F407xx Figure 4. Compatible board design between STM32F1xx/STM32F4xx: LQFP64 Doc ID 022152 Rev 1 Description Ω 15/154 ...
Page 16
Description 2.2 Device overview Figure 5. STM32F40x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked from TIMxCLK MHz. 16/154 Doc ID ...
Page 17
STM32F405xx, STM32F407xx ® 2.2.1 ARM Cortex™-M4F core with embedded Flash and SRAM The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU ...
Page 18
Description 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to ...
Page 19
STM32F405xx, STM32F407xx Figure 6. Multi-AHB matrix 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB ...
Page 20
Description The DMA can be used with the main peripherals: 2 ● SPI and ● ● USART ● General-purpose, basic and advanced-control timers TIMx ● DAC ● SDIO ● Camera interface (DCMI) ● ADC. 2.2.9 ...
Page 21
STM32F405xx, STM32F407xx pulse width shorter than the Internal APB2 clock period 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the ...
Page 22
Description 2.2.15 Power supply supervisor The power supply supervisor is enabled by holding PDR_ON high. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, BOR is always ...
Page 23
STM32F405xx, STM32F407xx V minimum value is 1 There are three low-power modes: – used in the nominal regulation mode (Run) – LPR is used in the Stop modes – Power-down is used in Standby mode: the ...
Page 24
Description Regulator OFF This mode allows to power the device as soon as V ● Regulator OFF/internal reset ON This mode is available only on UFBGA package activated by setting BYPASS_REG and PDR_ON pins to V The regulator ...
Page 25
STM32F405xx, STM32F407xx Figure 8. Startup in regulator OFF: slow V - power-down reset risen after V 1. This figure is valid both whatever the internal reset mode (on or off). Figure 9. Startup in regulator OFF mode: fast V - ...
Page 26
Description It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 32 kHz. The RTC can ...
Page 27
STM32F405xx, STM32F407xx Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a ...
Page 28
Description Table 3. Timer feature comparison Counter Counter Timer type Timer resolution Advanced- TIM1, 16-bit control TIM8 Up/down TIM2, 32-bit TIM5 Up/down TIM3, 16-bit TIM4 Up/down TIM9 16-bit General purpose TIM10, 16-bit TIM11 TIM12 16-bit TIM13, 16-bit TIM14 TIM6, Basic ...
Page 29
STM32F405xx, STM32F407xx General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 3 for differences). ● TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and ...
Page 30
Description SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: ● A 24-bit downcounter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0 ● ...
Page 31
STM32F405xx, STM32F407xx Table 4. USART feature comparison USART Standard Modem LIN name features (RTS/CTS) USART1 X X USART2 X X USART3 X X USART4 X - USART5 X - USART6 X X 2.2.23 Serial peripheral interface (SPI) The STM32F40x feature ...
Page 32
Description 2.2.25 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I achieve error-free I performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I disabling the main PLL (PLL) used for ...
Page 33
STM32F405xx, STM32F407xx The STM32F407xx includes the following features: ● Supports 10 and 100 Mbit/s rates ● Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F46x reference manual for details) ● Tagged MAC frame ...
Page 34
Description 2.2.28 Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames ...
Page 35
STM32F405xx, STM32F407xx The major features are: ● Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing ● Supports the session request protocol (SRP) and host negotiation protocol (HNP) ● 6 bidirectional endpoints ● 12 ...
Page 36
Description 2.2.34 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of ...
Page 37
STM32F405xx, STM32F407xx Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and ...
Page 38
Pinouts and pin description 3 Pinouts and pin description Figure 10. STM32F40x LQFP64 pinout 38/154 ...
Page 39
STM32F405xx, STM32F407xx Figure 11. STM32F40x LQFP100 pinout Doc ID 022152 Rev 1 Pinouts and pin description 39/154 ...
Page 40
Pinouts and pin description Figure 12. STM32F40x LQFP144 pinout 40/154 Doc ID 022152 Rev 1 STM32F405xx, STM32F407xx ...
Page 41
STM32F405xx, STM32F407xx Figure 13. STM32F40x LQFP176 pinout Doc ID 022152 Rev 1 Pinouts and pin description 41/154 ...
Page 42
Pinouts and pin description Figure 14. STM32F40x UFBGA176 ballout 42/154 Doc ID 022152 Rev 1 STM32F405xx, STM32F407xx ...
Page 43
STM32F405xx, STM32F407xx Table 5. STM32F40x pin and ball definitions Pins Pin name - ...
Page 44
Pinouts and pin description Table 5. STM32F40x pin and ball definitions (continued) Pins Pin name - ...
Page 45
STM32F405xx, STM32F407xx Table 5. STM32F40x pin and ball definitions (continued) Pins Pin name - - ...
Page 46
Pinouts and pin description Table 5. STM32F40x pin and ball definitions (continued) Pins Pin name R14 R15 P15 P14 N15 98 ...
Page 47
STM32F405xx, STM32F407xx Table 5. STM32F40x pin and ball definitions (continued) Pins Pin name 48 75 108 G13 127 - - - E12 128 - - - E13 129 - - - D13 130 - - - E14 131 - - ...
Page 48
... Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F46x reference manual, available from the STMicroelectronics website: www.st.com. ...
Page 49
Table 6. Alternate function mapping AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 TIM2_CH1 PA0 TIM 5_CH1 TIM8_ETR TIM2_ETR PA1 TIM2_CH2 TIM5_CH2 PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 PA4 TIM2_CH1 PA5 TIM8_CH1N TIM2_ETR PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN ...
Page 50
Table 6. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PB15 RTC_50Hz TIM1_CH3N TIM8_CH3N PC0 PC1 PC2 PC3 PC4 PC5 PC6 TIM3_CH1 TIM8_CH1 PC7 TIM3_CH2 TIM8_CH2 PC8 TIM3_CH3 TIM8_CH3 PC9 MCO2 TIM3_CH4 TIM8_CH4 PC10 PC11 ...
Page 51
Table 6. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PD15 TIM4_CH4 PE0 TIM4_ETR PE1 PE2 TRACECLK PE3 TRACED0 PE4 TRACED1 PE5 TRACED2 TIM9_CH1 PE6 TRACED3 TIM9_CH2 PE7 TIM1_ETR PE8 TIM1_CH1N PE9 TIM1_CH1 PE10 TIM1_CH2N ...
Page 52
Table 6. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PG8 PG9 PG10 PG11 PG12 PG13 PG14 PG15 PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PH8 ...
Page 53
Table 6. Alternate function mapping (continued) AF0 AF1 AF2 AF3 Port SYS TIM1/2 TIM3/4/5 TIM8/9/10/11 PH15 TIM8_CH3N PI0 TIM5_CH4 PI1 PI2 TIM8_CH4 PI3 TIM8_ETR PI4 TIM8_BKIN PI5 TIM8_CH1 PI6 TIM8_CH2 PI7 TIM8_CH3 PI8 PI9 PI10 PI11 AF4 AF5 AF6 AF7 ...
Page 54
Memory map 4 Memory map The memory map is shown in Figure 15. Memory map 54/154 Figure 15. Doc ID 022152 Rev 1 STM32F405xx, STM32F407xx ...
Page 55
STM32F405xx, STM32F407xx 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
Page 56
Electrical characteristics 5.1.6 Power supply scheme Figure 18. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate ...
Page 57
STM32F405xx, STM32F407xx 5.1.7 Current consumption measurement Figure 19. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 8: Current characteristics, and damage to the device. These are stress ratings only and functional ...
Page 58
Electrical characteristics Table 8. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...
Page 59
STM32F405xx, STM32F407xx Table 10. General operating conditions Symbol Parameter V Backup operating voltage BAT V When the internal regulator is ON, CAP1 V and V CAP_1 CAP_2 connect a stabilization capacitor. When the internal regulator is OFF V (BYPASS_REG connected ...
Page 60
Electrical characteristics Table 11. Limitations depending on the operating power supply range Maximum Operating power ADC supply operation range frequency (f 16 MHz with Conversion V =1 time up to (2) 2.1 V memory wait 1.2 Msps 18 ...
Page 61
STM32F405xx, STM32F407xx 5.3.2 VCAP1/VCAP2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor C the VCAP1/VCAP2 pins. C Figure 20. External capacitor C 1. Legend: ESR is the equivalent series resistance. Table 12. VCAP1/VCAP2 operating ...
Page 62
Electrical characteristics 5.3.5 Embedded reset and power control block characteristics The parameters given in temperature and V Table 15. Embedded reset and power control block characteristics Symbol Programmable voltage V PVD detector level selection (3) V PVD hysteresis PVDhyst Power-on/power-down ...
Page 63
STM32F405xx, STM32F407xx Table 15. Embedded reset and power control block characteristics Symbol Brownout level 1 V BOR1 threshold Brownout level 2 V BOR2 threshold Brownout level 3 V BOR3 threshold (3) V BOR hysteresis BORhyst (3)(4) T Reset temporization RSTTEMPO ...
Page 64
Electrical characteristics from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to 168 MHz,). ● When the peripherals are enabled HCLK is the system clock PCLK2 ...
Page 65
STM32F405xx, STM32F407xx Table 17. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM Symbol Parameter Supply current Run mode 1. Code and data processing running ...
Page 66
Electrical characteristics Table 18. Typical and maximum current consumption in Sleep mode Symbol Parameter External clock all peripherals enabled Supply current Sleep mode External clock peripherals disabled 1. TBD stands for “to be defined”. 2. Based on ...
Page 67
STM32F405xx, STM32F407xx Table 19. Typical and maximum current consumptions in Stop mode Symbol Parameter Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode with main Flash in ...
Page 68
Electrical characteristics Table 21. Typical and maximum current consumptions in V Symbol Parameter Backup SRAM ON, RTC ON Backup SRAM OFF, low-speed Backup oscillator and RTC ON I domain supply DD_VBAT current Backup SRAM ON, RTC OFF Backup SRAM OFF, ...
Page 69
STM32F405xx, STM32F407xx where I is the current sunk by a switching I/O to charge/discharge the capacitive load the MCU supply voltage the /O switching frequency the total capacitance seen by the ...
Page 70
Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in under the following conditions: ● At startup, all I/O pins are configured as analog pins by firmware. ● All peripherals are disabled unless otherwise ...
Page 71
STM32F405xx, STM32F407xx Table 23. Peripheral current consumption Peripheral APB1 (1) (continued) (2) Typical consumption at 25 °C TIM2 TIM3 TIM4 TIM5 TIM6 TIM7 TIM12 TIM13 TIM14 USART2 USART3 UART4 UART5 I2C1 I2C2 I2C3 SPI2 SPI3 CAN1 CAN2 (3) DAC channel ...
Page 72
Electrical characteristics Table 23. Peripheral current consumption Peripheral APB2 1. TBD stands for “to be defined”. 2. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 3. EN1 bit is set in DAC_CR register. ...
Page 73
STM32F405xx, STM32F407xx 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in external clock source, and under ambient temperature and supply voltage conditions summarized in Table Table 25. High-speed external user clock ...
Page 74
Electrical characteristics Figure 21. High-speed external clock source AC timing diagram V HSEH 90% 10% V HSEL t r(HSE) External clock source Figure 22. Low-speed external clock source AC timing diagram V LSEH 90% 10% V LSEL t r(LSE) External ...
Page 75
STM32F405xx, STM32F407xx Table 27. HSE 4-26 MHz oscillator characteristics Symbol f Oscillator frequency OSC_IN R Feedback resistor F Recommended load capacitance C versus equivalent serial resistance of the crystal (R i HSE driving current 2 g Oscillator transconductance m (4) ...
Page 76
Electrical characteristics Table 28. LSE oscillator characteristics (f Symbol R Feedback resistor F Recommended load capacitance (3) C versus equivalent serial resistance of the crystal (R I LSE driving current 2 g Oscillator Transconductance m (5) t startup time SU(LSE) ...
Page 77
STM32F405xx, STM32F407xx 5.3.9 Internal clock source characteristics The parameters given in ambient temperature and V High-speed internal (HSI) RC oscillator Low-speed internal (LSI) RC oscillator Table 29. HSI oscillator characteristics Symbol Parameter f Frequency HSI Accuracy of the HSI ACC ...
Page 78
Electrical characteristics Figure 25. ACC 5.3.10 PLL characteristics The parameters given in temperature and V Table 31. Main PLL characteristics Symbol Parameter (1) f PLL input clock PLL_IN f PLL multiplier output clock PLL_OUT 48 MHz PLL multiplier output f ...
Page 79
STM32F405xx, STM32F407xx Table 31. Main PLL characteristics (continued) Symbol Parameter Cycle-to-cycle jitter Period Jitter (4) Jitter Main clock output (MCO) for RMII Ethernet Main clock output (MCO) for MII Ethernet Bit Time CAN jitter Main clock output (MCO) for RMMI ...
Page 80
Electrical characteristics Table 32. PLLI2S (audio PLL) characteristics Symbol Parameter Master I2S clock jitter (5) Jitter WS I2S clock jitter PLLI2S power consumption on (6) I DD(PLLI2S PLLI2S power consumption on (6) I DDA(PLLI2S) V DDA 1. TBD ...
Page 81
STM32F405xx, STM32F407xx 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 33. SSCG parameters constraint Symbol f Mod md MODEPER * INCSTEP 1. Guaranteed by design, not ...
Page 82
Electrical characteristics Figure 26 and Figure 27 down spread modes, where PLL_OUT T is the modulation period. mode md is the modulation depth. Figure 26. PLL output clock waveforms in center spread mode Figure 27. PLL output ...
Page 83
STM32F405xx, STM32F407xx Table 35. Flash memory programming Symbol t Word programming time prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ERASE128KB t Mass erase time ME V ...
Page 84
Electrical characteristics Table 36. Flash memory programming with V Symbol t Double word programming prog t Sector (16 KB) erase time ERASE16KB t Sector (64 KB) erase time ERASE64KB t Sector (128 KB) erase time ERASE128KB t Mass erase time ...
Page 85
STM32F405xx, STM32F407xx A device reset allows normal operations to be resumed. The test results are given in defined in application note AN1709. Table 38. EMS characteristics Symbol Voltage limits to be applied on any I/O pin to V FESD induce ...
Page 86
Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC standard which specifies the test board and the pin loading. Table 39. EMI characteristics Symbol Parameter V = 3.3 V, ...
Page 87
STM32F405xx, STM32F407xx Static latchup Two complementary static tests are required on six parts to assess the latchup performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and ...
Page 88
Electrical characteristics 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in performed under the conditions summarized in compliant. Table 43. I/O static characteristics Symbol Parameter V Input low level voltage IL (2) TT I/O input ...
Page 89
STM32F405xx, STM32F407xx All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, ...
Page 90
Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Table 45, respectively. Unless otherwise specified, the parameters given in performed under the ambient temperature and V in Table 10. Table 45. I/O AC ...
Page 91
STM32F405xx, STM32F407xx Table 45. I/O AC characteristics OSPEEDRy [1:0] bit Symbol (1) value F Maximum frequency max(IO)out 11 Output high to low level fall t f(IO)out time Output low to high level rise t r(IO)out time Pulse width of external ...
Page 92
Electrical characteristics 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology connected to a permanent pull-up resistor, R (see PU Unless otherwise specified, the parameters given in performed under the ambient temperature and V in ...
Page 93
STM32F405xx, STM32F407xx 5.3.18 TIM timer characteristics The parameters given in Refer to Section 5.3.16: I/O port characteristics function characteristics (output compare, input capture, external clock, PWM output). Table 47. Characteristics of TIMx connected to the APB1 domain Symbol t Timer ...
Page 94
Electrical characteristics Table 48. Characteristics of TIMx connected to the APB2 domain Symbol t Timer resolution time res(TIM) Timer external clock f EXT frequency on CH1 to CH4 Res Timer resolution TIM 16-bit counter clock t period when internal clock ...
Page 95
STM32F405xx, STM32F407xx 2 Table 49 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t ...
Page 96
Electrical characteristics 2 Figure 30 bus AC waveforms and measurement circuit 1. Measurement points are done at CMOS levels: 0.3V Table 50. SCL frequency ( External pull-up resistance For speeds around 200 ...
Page 97
STM32F405xx, STM32F407xx SPI interface characteristics Unless otherwise specified, the parameters given in are derived from tests performed under the ambient temperature, f supply voltage conditions summarized in Refer to Section 5.3.16: I/O port characteristics function characteristics ...
Page 98
Electrical characteristics Figure 31. SPI timing diagram - slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...
Page 99
STM32F405xx, STM32F407xx Figure 33. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are done at CMOS levels: 0.3V (1) ...
Page 100
Electrical characteristics 2 Table 52 characteristics Symbol clock frequency 1/t c(CK r(CK clock rise and fall time t f(CK) ( valid time v(WS) ( hold ...
Page 101
STM32F405xx, STM32F407xx 2 Figure 34 slave timing diagram (Philips protocol) CPOL = 0 CPOL = 1 WS input SD transmit SD receive 1. Measurement points are done at CMOS levels: 0.3 × LSB transmit/receive of the ...
Page 102
Electrical characteristics USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Spee the USB OTG HS and USB OTG FS controllers. Table 53. USB OTG FS startup time Symbol (1) t STARTUP 1. Guaranteed by design, not tested ...
Page 103
STM32F405xx, STM32F407xx Figure 36. USB OTG FS timings: definition of data signal rise and fall time Differen tial data lines V CRS Table 55. USB OTG FS electrical characteristics Symbol t Rise time r t Fall time ...
Page 104
Electrical characteristics USB HS characteristics Table 57 shows the USB HS operating voltage. Table 57. USB HS DC electrical characteristics Symbol Input level V 1. All the voltages are measured from the local ground potential. Table 58. USB HS clock ...
Page 105
STM32F405xx, STM32F407xx Table 59. ULPI timing Setup time (control in) Output clock Hold time (control in) Output delay (control out) Setup time (control in) Input clock Hold time (control in) (optional) Output delay (control out 2.7 V ...
Page 106
Electrical characteristics Table 62 gives the list of Ethernet MAC signals for the RMII and corresponding timing diagram. Figure 39. Ethernet RMII timing diagram RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV Table 62. Dynamics characteristics: Ethernet MAC signals for RMII Symbol t ...
Page 107
STM32F405xx, STM32F407xx Table 63. Dynamics characteristics: Ethernet MAC signals for MII Symbol t Receive data setup time su(RXD) t Receive data hold time ih(RXD) t Data valid setup time su(DV) t Data valid hold time ih(DV) t Error setup time ...
Page 108
Electrical characteristics Table 64. ADC characteristics Symbol Parameter (5) t Sampling time S (5) t Power-up time STAB Total conversion time (including (5) t CONV sampling time) Sampling rate ( MHz) ADC ADC V DC ...
Page 109
STM32F405xx, STM32F407xx Equation 1: R AIN The formula above allowed for an error below 1/4 of LSB (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. a Table 65. ADC ...
Page 110
Electrical characteristics Figure 41. ADC accuracy characteristics 1. See also Table 65. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line Total Unadjusted Error: maximum deviation between the actual and ...
Page 111
STM32F405xx, STM32F407xx General PCB design guidelines Power supply decoupling should be performed as shown in depending on whether V ceramic (good quality). They should be placed them as close as possible to the chip. Figure 43. Power supply and reference ...
Page 112
Electrical characteristics 5.3.21 Temperature sensor characteristics Table 66. TS characteristics Symbol ( linearity with temperature L SENSE (1) Avg_Slope Average slope (1) V Voltage at 25 °C 25 (2) t Startup time START (3)(2) T ADC sampling time ...
Page 113
STM32F405xx, STM32F407xx 5.3.24 DAC electrical characteristics Table 69. DAC characteristics Symbol Parameter V Analog supply voltage DDA V Reference supply voltage REF+ V Ground SSA (2) R Resistive load with buffer ON LOAD Impedance output with buffer ( ...
Page 114
Electrical characteristics Table 69. DAC characteristics (continued) Symbol Parameter Integral non linearity (difference between measured value at Code i (3) INL and the value at Code line drawn between Code 0 and last Code 1023) Offset error ...
Page 115
STM32F405xx, STM32F407xx Figure 45. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. ...
Page 116
Electrical characteristics 5.3.25 FSMC characteristics Asynchronous waveforms and timings Figure 46 through Table 73 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● AddressSetupTime = 0 ● AddressHoldTime = 1 ● ...
Page 117
STM32F405xx, STM32F407xx Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Symbol t FSMC_BL hold time after FSMC_NOE high h(BL_NOE) t Data to FSMC_NEx high setup time su(Data_NE) t Data to FSMC_NOEx high setup time su(Data_NOE) t Data hold time after FSMC_NOE ...
Page 118
Electrical characteristics Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Symbol t FSMC_NEx low to FSMC_A valid v(A_NE) t Address hold time after FSMC_NWE high h(A_NWE) t FSMC_NEx low to FSMC_BL valid v(BL_NE) t FSMC_BL hold time after FSMC_NWE high h(BL_NWE) ...
Page 119
STM32F405xx, STM32F407xx Table 72. Asynchronous multiplexed PSRAM/NOR read timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NOE low v(NOE_NE) t FSMC_NOE low time w(NOE) t FSMC_NOE high to FSMC_NE high hold time h(NE_NOE) t FSMC_NEx low to ...
Page 120
Electrical characteristics Figure 49. Asynchronous multiplexed PSRAM/NOR write waveforms FSMC_NEx FSMC_NOE FSMC_NWE FSMC_A[25:16] FSMC_NBL[1:0] FSMC_ AD[15:0] FSMC_NADV Table 73. Asynchronous multiplexed PSRAM/NOR write timings Symbol t FSMC_NE low time w(NE) t FSMC_NEx low to FSMC_NWE low v(NWE_NE) t FSMC_NWE low ...
Page 121
STM32F405xx, STM32F407xx Synchronous waveforms and timings Figure 50 through Table 77 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● BurstAccessMode = FSMC_BurstAccessMode_Enable; ● MemoryType = FSMC_MemoryType_CRAM; ● WriteBurst = FSMC_WriteBurst_Enable; ...
Page 122
Electrical characteristics Table 74. Synchronous multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) d(CLKL-NExH) t FSMC_CLK low to FSMC_NADV low ...
Page 123
STM32F405xx, STM32F407xx Figure 51. Synchronous multiplexed PSRAM write timings Doc ID 022152 Rev 1 Electrical characteristics 123/154 ...
Page 124
Electrical characteristics Table 75. Synchronous multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-ADV) t d(CLKL-ADIV) t d(CLKL-Data) t su(NWAITV-CLKH) t h(CLKH-NWAITV) t d(CLKL-NBLH) ...
Page 125
STM32F405xx, STM32F407xx Figure 52. Synchronous non-multiplexed NOR/PSRAM read timings Table 76. Synchronous non-multiplexed NOR/PSRAM read timings Symbol t FSMC_CLK period w(CLK) t FSMC_CLK low to FSMC_NEx low (x = 0...2) d(CLKL-NExL) t FSMC_CLK low to FSMC_NEx high (x = 0...2) ...
Page 126
Electrical characteristics Figure 53. Synchronous non-multiplexed PSRAM write timings Table 77. Synchronous non-multiplexed PSRAM write timings Symbol t w(CLK) t d(CLKL-NExL) t d(CLKL-NExH) t d(CLKL-NADVL) t d(CLKL-NADVH) t d(CLKL-AV) t d(CLKL-AIV) t d(CLKL-NWEL) t d(CLKL-NWEH) t d(CLKL-Data) t su(NWAITV-CLKH) t ...
Page 127
STM32F405xx, STM32F407xx PC Card/CompactFlash controller waveforms and timings Figure 54 through corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime ...
Page 128
Electrical characteristics Figure 55. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NREG FSMC_NIOWR FSMC_NIORD t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[15:0] 128/154 High t v(NCE4_1-A) t d(NREG-NCE4_1) t d(NIORD-NCE4_1) t w(NWE) MEMxHIZ =1 t v(NWE-D) Doc ID ...
Page 129
STM32F405xx, STM32F407xx Figure 56. PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG FSMC_NWE t d(NCE4_1-NOE) FSMC_NOE (1) FSMC_D[15:0] 1. Only data bits 0...7 are read (bits 8...15 are disregarded). t v(NCE4_1-A) High t ...
Page 130
Electrical characteristics Figure 57. PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD FSMC_NREG t d(NCE4_1-NWE) FSMC_NWE FSMC_NOE FSMC_D[7:0](1) 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 58. PC Card/CompactFlash controller ...
Page 131
STM32F405xx, STM32F407xx Figure 59. PC Card/CompactFlash controller waveforms for I/O space write access Table 78. Switching characteristics for PC Card/CF read and write cycles Symbol FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid ( v(NCEx-A) 0...10) FSMC_NCE4_1 low ...
Page 132
Electrical characteristics Table 78. Switching characteristics for PC Card/CF read and write cycles Symbol t FSMC_NIOWR low width w(NIOWR) t FSMC_NIOWR low to FSMC_D[15:0] valid v(NIOWR-D) t FSMC_NIOWR high to FSMC_D[15:0] invalid h(NIOWR-D) t FSMC_NCE4_1 low to FSMC_NIOWR valid d(NCE4_1-NIOWR) ...
Page 133
STM32F405xx, STM32F407xx Figure 60. NAND controller waveforms for read access Figure 61. NAND controller waveforms for write access Doc ID 022152 Rev 1 Electrical characteristics 133/154 ...
Page 134
Electrical characteristics Figure 62. NAND controller waveforms for common memory read access Figure 63. NAND controller waveforms for common memory write access Table 79. Switching characteristics for NAND Flash read and write cycles Symbol (3) t FSMC_D[15:0] valid before FSMC_NWE ...
Page 135
STM32F405xx, STM32F407xx Table 79. Switching characteristics for NAND Flash read and write cycles Symbol (4) t FSMC_ALE valid before FSMC_NWE low d(ALE-NWE) (4) t FSMC_NWE high to FSMC_ALE invalid h(NWE-ALE) (4) t FSMC_ALE valid before FSMC_NOE low d(ALE-NOE) (4) t ...
Page 136
Electrical characteristics Figure 65. SD default mode Table 81 MMC characteristics Symbol Clock frequency in data transfer f PP mode - SDIO_CK/f t Clock low time, f W(CKL) t Clock high time, f W(CKH) t Clock rise time ...
Page 137
STM32F405xx, STM32F407xx 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status ...
Page 138
Package characteristics Figure 66. LQFP64 – pin low-profile quad flat package outline Drawing is not to scale. 2. Dimensions are in millimeters. Table 83. LQFP64 – ...
Page 139
STM32F405xx, STM32F407xx Figure 68. LQFP100 100-pin low-profile quad flat package outline 100 Pin identification e 1. Drawing is not to scale. 2. Dimensions are in millimeters. ...
Page 140
Package characteristics Figure 70. LQFP144 mm, 144-pin low-profile quad flat package outline Seating plane ccc 108 109 144 Pin 1 1 identification 1. Drawing is not to scale. ...
Page 141
STM32F405xx, STM32F407xx Figure 72. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Seating plane Drawing is not to scale. Table 86. UFBGA176+25 - ultra thin ...
Page 142
Package characteristics Figure 73. LQFP176 mm, 144-pin low-profile quad flat package outline C Seating plane Pin 1 identification 1. Drawing is not to scale. Table 87. LQFP176 mm, 144-pin low-profile quad ...
Page 143
STM32F405xx, STM32F407xx 6.2 Thermal characteristics The maximum chip-junction temperature, T using the following equation: Where: max is the maximum ambient temperature in °C, ● Θ is the package junction-to-ambient thermal resistance, in °C/W, ● JA ● P max ...
Page 144
Part numbering 7 Part numbering Table 89. Ordering information scheme Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 405 = STM32F40x, connectivity, USB OTG FS/HS, 407= STM32F40x, connectivity, USB OTG FS/HS, camera interface, ...
Page 145
STM32F405xx, STM32F407xx Appendix A Application block diagrams A.1 Main applications versus package Table 90 gives examples of configurations for each package. Table 90. Main applications versus package for STM32F407xx microcontrollers 64 pins Config Config 1 2 OTG ...
Page 146
Application block diagrams A.2 Application example with regulator OFF Figure 74. Regulator OFF/internal reset ON 1. This mode is available only on UFBGA176 package. Figure 75. Regulator OFF/internal reset OFF 1. This mode is available only on UFBGA176 package. 146/154 ...
Page 147
STM32F405xx, STM32F407xx A.3 USB OTG full speed (FS) interface solutions Figure 76. USB OTG FS peripheral-only connection 1. External voltage regulator only needed when building a V Figure 77. USB OTG FS host-only connection 1. STMPS2141STR/STULPI01B needed only if the ...
Page 148
Application block diagrams Figure 78. OTG FS connection dual-role with internal PHY 1. External voltage regulator only needed when building STMPS2141STR/STULPI01B needed only if the application has to support a V basic power switch can be used ...
Page 149
STM32F405xx, STM32F407xx Figure 80. USB OTG HS host-only connection in FS mode 1. STMPS2141STR/STULPI01B needed only if the application has to support a V basic power switch can be used are available on the application board. Figure ...
Page 150
Application block diagrams A.5 Complete audio player solutions Two solutions are offered, illustrated in Figure 82 shows storage media to audio DAC/amplifier streaming using a software Codec. This solution implements an audio crystal to provide audio class I clock (0.5% ...
Page 151
STM32F405xx, STM32F407xx Figure 84. Audio player solution using PLL, PLLI2S, USB and 1 crystal Figure 85. Audio PLL (PLLI2S) providing accurate I2S clock 1 MHz CLKIN /M M=1,2,3,..,64 N=192,194,..,432 PLLI2S 192 to 432 MHz PhaseC VCO /N /R R=2,3,4,5,6,7 Doc ...
Page 152
Application block diagrams Figure 86. Master clock (MCK) used to drive the external audio DAC I2S_CK /I2SD 2,3,4,..,129 1. I2S_SCK is the I2S serial clock to the external audio DAC (not to be confused with I2S_CK). Figure 87. Master clock ...
Page 153
STM32F405xx, STM32F407xx Revision history Table 91. Document revision history Date Revision 15-Sep-2011 1 Initial release. Doc ID 022152 Rev 1 Revision history Changes 153/154 ...
Page 154
... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...