AD8186ARU Analog Devices Inc, AD8186ARU Datasheet - Page 14

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AD8186ARU

Manufacturer Part Number
AD8186ARU
Description
IC MULTIPLEXER TRPL 2X1 24TSSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8186ARU

Rohs Status
RoHS non-compliant
Function
Multiplexer
Circuit
3 x 2:1
On-state Resistance
350 mOhm
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
3.5 V ~ 5.5 V
Current - Supply
15mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP (0.173", 4.40mm Width)
AD8186/AD8187
AC-Coupled Inputs (DC Restore before Mux Input)
Using ac-coupled inputs presents an interesting challenge for video
systems operating from a single 5 V supply. In NTSC and PAL
video systems, 700 mV is the approximate difference between the
maximum signal voltage and black level. It is assumed that sync
has been stripped. However, given the two pathological cases
shown in Figure 7, a dynamic range of twice the maximum signal
swing is required if the inputs are to be ac-coupled. A possible
solution would be to use a dc restore circuit before the mux.
Tolerance to Capacitive Load
Op amps are sensitive to reactive loads. A capacitive load at the
output appears in parallel with an effective resistance of R
(R
loop output impedance, approximately 15 Ω for these muxes.
The load pole, at f
phase margin and therefore stability. The old workaround is to
place a small series resistance directly at the output to isolate the
load pole. While effective, this ruse also affects the dc and termina-
tion characteristics of a 75 Ω system. The AD8186 and AD8187
are built with a variable compensation scheme that senses the
output reactance and trades bandwidth for phase margin, ensuring
faster settling and lower overshoot at higher capacitive loads.
Secondary Supplies and Supply Bypassing
The high current output transistors are given their own supply
pins (Pins 15, 17, 19, and 21) to reduce supply noise on-chip
and to improve output isolation. Since these secondary, high
current supply pins are not connected on-chip to the primary
analog supplies (V
care should be taken to ensure that the supply bypass capacitors
are connected to the correct pins. At a minimum, the primary
supplies should be bypassed. Pin 6 and Pin 7 may be a convenient
place to accomplish this. Stacked power and ground planes could
be a convenient way to bypass the high current supply pins.
L
r
O
), where R
Figure 7. Pathological Case for
Input Dynamic Range
V
REF
BLACK LINE WITH WHITE PIXEL
+700mV
V
SIGNAL
L
is the discrete resistive load, and r
LOAD
CC
/V
= 1/(2 R
EE
GND
, Pins 6, 7, 9, 11, 13, and 24), some
+5 V
V
AVG
V
EFF
WHITE LINE WITH BLACK PIXEL
AVG
C
V
V
V
SET BY THE RESISTORS
L
INPUT
REF
REF
), can seriously degrade
~ V
IS A DC VOLTAGE
= V
AVG
REF
+ V
–700mV
O
is the open-
SIGNAL
V
REF
EFF
=
–14–
Split-Supply Operation
Operating from split supplies (e.g., +3 V/–2 V or ± 2.5 V) simpli-
fies the selection of the V
voltage. In this case, it is convenient to tie V
The logic inputs are level shifted internally to allow the digital
supplies and logic inputs to operate from 0 V and 5 V when
powering the analog circuits from split supplies. The maximum
voltage difference between DV
(see Figure 9).
Figure 8. Detail of Primary and Secondary Supplies
0.1 F
(+5)
(0V)
DIGITAL SUPPLIES
Figure 9. Split-Supply Operation
1 F
D
IN2A
IN0A
IN1A
V
IN0B
IN2B
IN1B
GND
V
V
REF
V
V
CC
EE
EE
EE
DV
D
SPLIT-SUPPLY OPERATION
10
11
GND
12
1
2
3
4
5
6
7
8
9
CC
REF
voltage and load resistor termination
CC
8V MAX
and V
MUX1
MUX2
(+2.5)
MUX0
(–2.5)
ANALOG SUPPLIES
EE
must not exceed 8 V
REF
24
23
22
21
20
19
18
17
16
15
14
13
to ground.
V
OE
SEL A/B
V
OUT 0
V
OUT 1
V
OUT 2
V
DV
V
CC
CC
EE
CC
EE
CC
V
V
CC
CC
EE
REV. A

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