FST16232MEA Fairchild Semiconductor, FST16232MEA Datasheet - Page 4

• Manufacturer Part Number: FST16232MEA
• Manufacturer: Fairchild Semiconductor

Specifications of FST16232MEA

• Logic Family: FST
• Number Of Bits: 32
• Number Of Elements: 1
• Technology: CMOS
• Low Level Output Current: 128mA
• On Resistance: 11Ohm
• Propagation Delay Time: 9ns
• Package Type: SSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Quiescent Current: 3uA
• Pin Count: 56
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

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C
C
f
t
t
t
t
t
t
t
MAX
PHL
PHL
PZH
PHZ
S
H
W
AC Electrical Characteristics
Note 6: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Note 7: T
AC Loading and Waveforms
Note: Input driven by 50
Note: C
Note: Input PRR
IN
I/O
Symbol
, t
, t
Symbol
, t
, t
PLH
PLH
PZL
PLZ
L
A
includes load and stray capacitance
Maximum Clock Frequency
Prop Delay Bus to Bus (Note 6)
Prop Delay CLK to B or A
Output Enable Time
CLK to A
Output Enable Time
CLK to A or B
Output Disable Time
CLK to A or B
Setup Time S
Setup Time CLKEN before CLK
Hold Time S
Hold Time CLKEN after CLK
Pulse Width
25 C, f
Parameter
Control pin Input Capacitance
Input/Output Capacitance
1.0 MHz, t
1 MHz, Capacitance is characterized but not tested.
B
Parameter
1
source terminated in 50
1
(Note 7)
, S
1
1
, S
W
or B
0
B
0
after CLK
2
500 ns
before CLK
2
V
Min
150
2.0
1.7
2.0
1.0
2.5
1.8
1.0
1.5
3.1
CC
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
C
4.5 – 5.5V
L
T
A
50pF, RU
Max
0.25
6.3
8.5
6.5
8.5
40 C to 85 C,
4
Typ
7
4
RD
Min
150
2.8
2.0
1.0
1.5
3.1
V
CC
500
Max
4.0V
Max
0.25
6.0
9.0
6.5
9.0
Units
pF
pF
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
V
V
CC
CC
V
V
V
V
V
V
V
V
V
Clock HIGH or LOW
I
I
I
I
I
I
I
I
I
5.0V
5.0V, S
OPEN
OPEN
OPEN
7V for t
OPEN for t
7V for t
OPEN for t
7V for t
OPEN for t
Conditions
0
Conditions
, S
PZL
PZL
PLZ
1
,
,
,
PZH
PZH
PHZ
0V
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure 1
Figure 2
Figure
No.