AT89C5131A-RDTIM Atmel, AT89C5131A-RDTIM Datasheet - Page 27
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AT89C5131A-RDTIM
Manufacturer Part Number
AT89C5131A-RDTIM
Description
C5131A 32K FLASH USB VQFP64 IND, 5V
Manufacturer
Atmel
Datasheet
1.AT89C5131A-RDTIM.pdf
(176 pages)
- Current page: 27 of 176
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External Bus Cycles
4136C–USB–04/05
Figure 12. External Code Memory Interface Structure
Table 33. External Data Memory Interface Signals
This section describes the bus cycles the AT89C5131 executes to fetch code (see
Figure 13) in the external program/code memory.
External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further
information on X2 mode (see the clock Section).
For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized
form and do not provide precise timing information.
Figure 13. External Code Fetch Waveforms
CPU Clock
Signal
Name
AD7:0
PSEN
A15:8
ALE
PSEN
ALE
P0
P2
Type
I/O
PCH
D7:0
O
O
O
Description
Address Lines
Upper address lines for the external bus.
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
Address Latch Enable
ALE signals indicates that valid address information are available on lines
AD7:0.
Program Store Enable Output
This signal is active low during external code fetch or external code read
(MOVC instruction).
AT89C5130A/
AT89C5131
PSEN
ALE
PCL
P2
P0
AD7:0
PCH
A15:8
Latch
D7:0
A7:0
A15:8
A7:0
D7:0
OE
PCL
EEPROM
Flash
AT89C5131
PCH
D7:0
Alternate
Function
P2.7:0
P0.7:0
-
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