P89LPC9321FN NXP Semiconductors, P89LPC9321FN Datasheet - Page 23
P89LPC9321FN
Manufacturer Part Number
P89LPC9321FN
Description
MCU 8-Bit 89LP 80C51 CISC 8KB Flash 2.5V/3.3V 28-Pin PDIP Tube
Manufacturer
NXP Semiconductors
Datasheet
1.P89LPC9321FN.pdf
(70 pages)
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NXP Semiconductors
P89LPC9321_1
Product data sheet
Fig 6.
Block diagram of oscillator control
(7.3728 MHz/14.7456 MHz
WITH CLOCK DOUBLER
7.10 CCLK wake-up delay
7.11 CCLK modification: DIVM register
7.12 Low power select
XTAL1
XTAL2
RC OSCILLATOR
(400 kHz
The P89LPC9321 has an internal wake-up timer that delays the clock until it stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus
60 s to 100 s. If the clock source is the internal RC oscillator, the delay is 200 s to
300 s. If the clock source is watchdog oscillator or external clock, the delay is
32 OSCCLK cycles.
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
The P89LPC9321 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is
8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power
consumption further. On any reset, CLKLP is logic 0 allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
OSCILLATOR
WATCHDOG
MEDIUM FREQUENCY
HIGH FREQUENCY
LOW FREQUENCY
5 %)
1 %)
TIMER 0 AND
RCCLK
TIMER 1
Rev. 01 — 9 December 2008
8-bit microcontroller with accelerated two-clock 80C51 core
I
2
C-BUS
OSCCLK
PCLK
DIVM
SPI
CCLK
PCLK
2
UART
P89LPC9321
WDT
RTC
CPU
32
CCU
PLL
002aae108
© NXP B.V. 2008. All rights reserved.
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