DS21354L+ Maxim Integrated Products, DS21354L+ Datasheet
DS21354L+
Specifications of DS21354L+
Related parts for DS21354L+
DS21354L+ Summary of contents
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GENERAL DESCRIPTION The DS21354/DS213554 single-chip (SCTs) contain all the necessary functions to connect to E1 lines. The devices are upward-compatible versions of the DS2153 and DS2154 SCTs. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an ...
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INTRODUCTION.................................................................................................................. 6 1. UNCTIONAL ESCRIPTION 1.2. DOCUMENT REVISION HISTORY .............................................................................................................8 2. BLOCK DIAGRAM .............................................................................................................. 9 3. PIN DESCRIPTION............................................................................................................ 10 3.1. PIN FUNCTION DESCRIPTION ................................................................................................................14 3.1.1. Transmit-Side Pins..............................................................................................................................14 3.1.2. Receive-Side Pins...............................................................................................................................17 3.1.3. Parallel Control Port Pins ....................................................................................................................20 3.1.4. ...
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ELASTIC STORES OPERATION...................................................................................... 65 12.1. RECEIVE SIDE .......................................................................................................................................65 12.2. TRANSMIT SIDE.....................................................................................................................................65 13. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................. 66 13.1. HARDWARE SCHEME ...........................................................................................................................66 13.2. INTERNAL REGISTER SCHEME BASED ON DOUBLE FRAME .........................................................66 13.3. INTERNAL REGISTER SCHEME BASED ...
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Figure 2-1. DS21354/554 Block Diagram ............................................................................................................................. 9 Figure 15-1. Basic External Analog Connections .............................................................................................................. 83 Figure 15-2. Optional Crystal Connection........................................................................................................................... 83 Figure 15-3. Jitter Tolerance................................................................................................................................................. 84 Figure 15-4. Jitter Attenuation .............................................................................................................................................. 84 Figure 15-5. Transmit Waveform Template ........................................................................................................................ 85 Figure ...
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Table 3-1. Pin Description Sorted by Pin Number............................................................................................................. 10 Table 3-2. Pin Description by Symbol ................................................................................................................................. 12 Table 4-1. Register Map Sorted by Address ...................................................................................................................... 25 Table 5-1. Device ID Bit Map ................................................................................................................................................ 30 Table 5-2. SYNC/RESYNC Criteria ..................................................................................................................................... 32 ...
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INTRODUCTION The DS21354/DS21554 are superset versions of the popular DS2153 and DS2154 SCTs offering the new features listed below. All the original features of the DS2153 and DS2154 have been retained, and the software created for the original devices ...
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Functional Description 1.1. The analog AMI/HDB3 waveform off the E1 line is transformer coupled into the RRING and RTIP pins of the DS21354/554. The device recovers clock and data from the analog signal and passes it through the jitter attenuation ...
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Document Revision History 1.2. REVISION 012799 Initial release Corrected TSYSCLK and RSYSCLK timing and added 4.096MHz and 8.192MHz 012899 timing 020399 Corrected definition and label of TUDR bit in the THIR register. 021199 Corrected address of IBO register in text. ...
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BLOCK DIAGRAM Figure 2-1. DS21354/554 Block Diagram CI RPOSI RCLKI RNEGI RNEGO RCLKO RPOSO 8XCLK 16.384 MHz XTALD MCLK DS21354/ DS21554 Framer Loopback Remote Loopback Jitter Attenuator Either transmit or receive path Local Loopback Receive Line I/F Clock / ...
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PIN DESCRIPTION Table 3-1. Pin Description Sorted by Pin Number PIN NAME 1 RCHBLK 2 JTMS 3 8MCLK 4 JTCLK 5 JTRST 6 RCL 7 JTDI 8, 9, 15, 23, 26, 27, N. JTDO 11 BTS 12 ...
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PIN NAME TYPE 49 TESO O 50 TDATA 51 TSYSCLK 52 TSSYNC 53 TCHCLK MUX 56 D0/AD0 I/O 57 D1/AD1 I/O 58 D2/AD2 I/O 59 D3/AD3 I/O 62 D4/AD4 I/O 63 D5/AD5 I/O 64 D6/AD6 ...
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Table 3-2. Pin Description by Symbol PIN NAME 3 8MCLK 13 8XCLK ALE (AS)/A7 11 BTS D0/AD0 57 ...
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PIN NAME 78 RLINK 99 RLOS/LOTC 96 RMSYNC 87 RNEGI 90 RNEGO 86 RPOSI 91 RPOSO 17 RRING 95 RSER 94 RSIG 93 RSIGF 98 RSYNC 100 RSYSCLK 16 RTIP 18 RVDD 19, 20, 24 RVSS 33 TCHBLK 53 TCHCLK ...
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Pin Function Description 3.1. 3.1.1. Transmit-Side Pins Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: ...
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Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into any combination of the Sa bit positions (Sa4 to Sa8). See Section ...
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Signal Name: TNEGO Signal Description: Transmit Negative Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally tied to TNEGI. Signal Name: TCLKO Signal Description: ...
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Receive-Side Pins Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output Updated with the fully recovered E1 data stream on the rising edge of RCLK. Signal Name: RLCLK Signal Description: Receive Link Clock Signal Type: Output 4kHz ...
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Signal Name: RFSYNC Signal Description: Receive Frame Sync Signal Type: Output An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries. Signal Name: RMSYNC Signal Description: Receive Multiframe Sync Signal Type: Output If the ...
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Signal Name: 8MCLK Signal Description: 8MHz Clock Signal Type: Output An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin. Signal Name: RPOSO Signal Description: Receive Positive Data Input Signal Type: Output Updated ...
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Parallel Control Port Pins Signal Name: INT Signal Description: Interrupt Signal Type: Output Active-low, open-drain output that flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the HDLC Status Register. ...
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Signal Name: RD (DS) Signal Description: Read Input—Data Strobe Signal Type: Input In Intel Mode, RD determines when data is read from the device. In Motorola Mode used to write to the device. See the Bus Timing Diagrams ...
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JTAG Test Access Port Pins JTRST Signal Name: Signal Description: IEEE 1149.1 Test Reset Signal Type: Input This signal is used to asynchronously reset the test access port controller. At power up, JTRST must be toggled from low to ...
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Line Interface Pins Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter ...
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Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 5.0V ±5% (DS21554) or 3.3V ±5% (DS21354). Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal ...
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PARALLEL PORT The DS21354/DS21554 are controlled through either a nonmultiplexed (MUX = multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. If ...
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ADDRESS TYPE 25 R/W Transmit Channel Blocking 4 26 R/W Transmit Idle 1 27 R/W Transmit Idle 2 28 R/W Transmit Idle 3 29 R/W Transmit Idle 4 2A R/W Transmit Idle Definition 2B R/W Receive Channel Blocking 1 2C ...
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ADDRESS TYPE 55 R/W Transmit Sa6 Bits 56 R/W Transmit Sa7 Bits 57 R/W Transmit Sa8 Bits 58 R Receive Si Bits Align Frame 59 R Receive Si Bits Non-Align Frame 5A R Receive Remote Alarm Bits 5B R Receive ...
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ADDRESS TYPE 85 R/W Receive Channel 6 86 R/W Receive Channel 7 87 R/W Receive Channel 8 88 R/W Receive Channel 9 89 R/W Receive Channel 10 8A R/W Receive Channel 11 8B R/W Receive Channel 12 8C R/W Receive ...
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ADDRESS TYPE B5 R/W Interleave Bus Operation Register B6 R/W Transmit HDLC Information Register B7 R/W Transmit HDLC FIFO Register B8 R/W Receive HDLC DS0 Control Register 1 B9 R/W Receive HDLC DS0 Control Register 2 BA R/W Transmit HDLC ...
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CONTROL, ID, AND TEST REGISTERS The operation of the DS21354/DS21554 is configured via a set of 10 control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, ...
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IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex) (MSB) T1E1 Bit 6 SYMBOL POSITION T1E1 IDR.7 Bit 6 IDR.6 Bit 5 IDR.5 Bit 4 IDR.4 ID3 IDR.3 ID2 IDR.1 ID1 IDR.2 ID0 IDR.0 RCR1: RECEIVE CONTROL REGISTER 1 (Address = ...
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Synchronization And Resynchronization 5.2. Once synchronization is accomplished there are certain criteria that can cause a resynchronization. These criteria are detailed in Table 5-2. Also see Table 5-2. SYNC/RESYNC Criteria FRAME OR MULTIFRAME SYNC CRITERIA LEVEL FAS FAS present in ...
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RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex) (MSB) Sa8S Sa7S SYMBOL POSITION Sa8S RCR2.7 Sa7S RCR2.6 Sa6S RCR2.5 Sa5S RCR2.4 Sa4S RCR2.3 RBCS RCR2.2 RESE RCR2.1 — RCR2.0 Sa6S Sa5S Sa4S NAME AND DESCRIPTION Sa8 Bit Select. Set ...
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TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex) (MSB) ODF TFPT T16S SYMBOL POSITION ODF TCR1.7 TFPT TCR1.6 T16S TCR1.5 TUA1 TCR1.4 TSiS TCR1.3 TSA1 TCR1.2 TSM TCR1.1 TSIO TCR1.0 Note: See Figure 18-15 for more details about how ...
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TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex) (MSB) Sa8S Sa7S SYMBOL POSITION Sa8S TCR2.7 Sa7S TCR2.6 Sa6S TCR2.5 Sa5S TCR2.4 Sa4S TCR2.3 ODM TCR2.2 AEBE TCR2.1 PF TCR2.0 Sa6S Sa5S Sa4S NAME AND DESCRIPTION Sa8 Bit Select. Set ...
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CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex) (MSB) FLB THDB3 TG802 SYMBOL POSITION FLB CCR1.7 THDB3 CCR1.6 TG802 CCR1.5 TCRC4 CCR1.4 RSM CCR1.3 RHDB3 CCR1.2 RG802 CCR1.1 RCRC4 CCR1.0 Framer Loopback 5.3. When CCR1.7 is set to one, ...
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CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex) (MSB) ECUS VCRFS AAIS SYMBOL POSITION ECUS CCR2.7 VCRFS CCR2.6 AAIS CCR2.5 ARA CCR2.4 RSERC CCR2.3 LOTCMC CCR2.2 RFF CCR2.1 RFE CCR2.0 ARA RSERC NAME AND DESCRIPTION Error Counter Update Select. ...
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Automatic Alarm Generation 5.4. The device can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive-side framer to determine if any of the following conditions are ...
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CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex) (MSB) TESE TCBFS TIRFS SYMBOL POSITION TESE CCR3.7 TCBFS CCR3.6 TIRFS CCR3.5 - CCR3.4 RSRE CCR3.3 THSE CCR3.2 TBCS CCR3.1 RCLA CCR3.0 — RSRE NAME AND DESCRIPTION Transmit-Side Elastic Store Enable ...
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CCR4: COMMON CONTROL REGISTER 4 (Address = A8 Hex) (MSB) RLB LLB LIAIS SYMBOL POSITION RLB CCR4.7 LLB CCR4.6 LIAIS CCR4.5 TCM4 CCR4.4 TCM3 CCR4.3 TCM2 CCR4.2 TCM1 CCR4.1 TCM0 CCR4.0 Remote Loopback 5.5. When CCR4.7 is set to a ...
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CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex) (MSB) LIRST RESA TESA SYMBOL POSITION LIRST CCR5.7 RESA CCR5.6 TESA CCR5.5 RCM4 CCR5.4 RCM3 CCR5.3 RCM2 CCR5.2 RCM1 CCR5.1 RCM0 CCR5.0 RCM4 RCM3 NAME AND DESCRIPTION Line Interface Reset. Setting ...
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CCR6: COMMON CONTROL REGISTER 6 (Address = 1D Hex) (MSB) LIUODO CDIG LIUSI SYMBOL POSITION LIUODO CCR6.7 CDIG CCR6.6 LIUSI CCR6.5 — CCR6.4 — CCR6.3 TCLKSRC CCR6.2 RESR CCR6.1 TESR CCR6.0 — — NAME AND DESCRIPTION Line Interface Open-Drain Option. ...
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STATUS AND INFORMATION REGISTERS The DS21354/DS21554 have a set of seven registers that contain information on the current real-time status of a framer—Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), Synchronizer Status Register (SSR), and ...
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RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex) (MSB) TESF TESE SYMBOL POSITION TESF RIR.7 TESE RIR.6 JALT RIR.5 RESF RIR.4 RESE RIR.3 CRCRC RIR.2 FASRC RIR.1 CASRC RIR.0 SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex) (MSB) CSC5 CSC4 ...
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CRC4 Sync Counter 6.1. The CRC4 Sync Counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by ...
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Table 6-1. Alarm Criteria ALARM RSA1 (Receive Signaling All Ones) RSA0 (Receive Signaling All Zeros) RDMA (Receive Distant Multiframe Alarm) RUA1 (Receive Unframed All Ones) RRA (Receive Remote Alarm) RCL (Receive Carrier Loss) SET CRITERIA over 16 consecutive frames (one ...
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SR2: STATUS REGISTER 2 (Address = 07 Hex) (MSB) RMF RAF SYMBOL POSITION RMF SR2.7 RAF SR2.6 TMF SR2.5 SEC SR2.4 TAF SR2.3 LOTC SR2.2 RCMF SR2.1 TSLIP SR2.0 TMF SEC TAF NAME AND DESCRIPTION Receive CAS Multiframe. Set every ...
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IMR1: INTERRUPT MASK REGISTER 1 (Address = 16 Hex) (MSB) RSA1 RDMA RSA0 SYMBOL POSITION NAME AND DESCRIPTION RSA1 IMR1.7 RDMA IMR1.6 RSA0 IMR1.5 RSLIP IMR1.4 RUA1 IMR1.3 RRA IMR1.2 RCL IMR1.1 RLOS IMR1.0 RSLIP RUA1 Receive Signaling All Ones/Signaling ...
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IMR2: INTERRUPT MASK REGISTER 2 (Address = 17 Hex) (MSB) RMF RAF SYMBOL POSITION RMF IMR2.7 RAF IMR2.6 TMF IMR2.5 SEC IMR2.4 TAF IMR2.3 LOTC IMR2.2 RCMF IMR2.1 TSLIP IMR2.0 TMF SEC TAF NAME AND DESCRIPTION Receive CAS Multiframe. 0 ...
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ERROR COUNT REGISTERS The DS21354/DS21554 have a set of four counters that record bipolar or code violations, errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. Each of ...
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CRC4 Error Counter 7.2. CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the maximum CRC4 ...
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FAS Error Counter 7.4. FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 12–bit counter that records word errors in the Frame Alignment Signal in time slot 0. This counter ...
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DS0 MONITORING FUNCTION Each framer in the DS21354/DS21554 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel ...
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TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address = A9 Hex) (MSB SYMBOL POSITION B1 TDS0M.7 B2 TDS0M.6 B3 TDS0M.5 B4 TDS0M.4 B5 TDS0M.3 B6 TDS0M.2 B7 TDS0M.1 B8 TDS0M.0 CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex) [Repeated ...
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RDS0M: RECEIVE DS0 MONITOR REGISTER (Address = AB Hex) (MSB SYMBOL POSITION B1 RDS0M.7 B2 RDS0M.6 B3 RDS0M.5 B4 RDS0M.4 B5 RDS0M.3 B6 RDS0M.2 B7 RDS0M.1 B8 RDS0M NAME AND DESCRIPTION Receive DS0 Channel Bit ...
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SIGNALING OPERATION The DS21354/DS21554 contain provisions for both processor-based (i.e., software-based) signaling bit access and for hardware-based access. Both the processor-based access and the hardware-based access can be used simultaneously if necessary. The processor-based signaling is covered in Section ...
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Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two time slots. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status ...
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TSRs before the old data is retransmitted. ITU specifications recommend that the ABCD signaling not be set to all zeros because they will emulate a CAS multiframe alignment word. The TS1 register is special because it contains the CAS ...
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Transmit Side Via the THSE control bit (CCR3.2), the DS21354/DS21554 can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at ...
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PER-CHANNEL CODE GENERATION AND LOOPBACK The DS21354/DS21554 can replace data on a channel-by-channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section 10.1. The ...
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TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex) (MSB) TIDR7 TIDR6 TIDR5 SYMBOL POSITION TIDR7 TIDR.7 TIDR0 TIDR.0 10.1.2. Per-Channel Code Insertion The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine which of the 32 ...
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Receive-Side Code Generation 10.2. On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the code ...
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CLOCK BLOCKING REGISTERS The receive-channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit-channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins, respectively. (The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual ...
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TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3 (MSB) CH18 CH3 CH17 CH22 CH7 CH21 CH26 CH11 CH25 CH30 CH15 CH29 *These bits should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and ...
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ELASTIC STORES OPERATION The DS21354/DS21554 contain dual two-frame (512 bits) elastic stores, one for the receive direction and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the ...
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ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION The DS21354/DS21554 provide for access to both the Sa and the Si bits through three different methods. The first method is accomplished via a hardware scheme using the RLINK/RLCLK and TLINK/TLCLK pins ...
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RAF: RECEIVE ALIGN FRAME REGISTER (Address = 2F Hex) (MSB SYMBOL POSITION Si RAF.7 0 RAF.6 0 RAF.5 1 RAF.4 1 RAF.3 0 RAF.2 1 RAF.1 1 RAF.0 RNAF: RECEIVE NON-ALIGN FRAME REGISTER (Address = 1F Hex) (MSB) ...
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TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address = 21 Hex) (MSB SYMBOL POSITION Si TNAF.7 1 TNAF.6 A TNAF.5 Sa4 TNAF.4 Sa5 TNAF.3 Sa6 TNAF.2 Sa7 TNAF.1 Sa8 TNAF.0 Note: Bit 6 of the TNAF register must be programmed ...
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TSaCR: TRANSMIT Sa BIT CONTROL REGISTER (Address = 1C Hex) (MSB) SiAF SiNAF SYMBOL POSITION SiAF TSaCR.7 SiNAF TSaCR.6 RA TSaCR.5 Sa4 TSaCR.4 Sa5 TSaCR.3 Sa6 TSaCR.2 Sa7 TSaCR.1 Sa8 TSaCR.0 RA Sa4 Sa5 NAME AND DESCRIPTION International Bit in ...
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HDLC CONTROLLER FOR THE Sa BITS OR DS0 The DS21354/DS21554 can extract/insert data from/into the Sa bit positions (Sa4 to Sa8) or from/to any multiple of DS0 or sub-DS0 channels. The SCT contains a complete HDLC controller (see Section ...
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HDLC Status Registers 14.2. Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a ...
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Basic Operation Details 14. basic guideline for interpreting and sending HDLC messages, the following sequences can be applied: 14.3.1. Example: Receive an HDLC Message 1. Enable RPS interrupts 2. Wait for interrupt to occur 3. Disable RPS interrupt ...
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HDLC Register Description 14.4. HCR: HDLC CONTROL REGISTER (Address = B0 Hex) (MSB) — RHR SYMBOL POSITION — HCR.7 RHR HCR.6 TFS HCR.5 THR HCR.4 TABT HCR.3 TEOM HCR.2 TZSD HCR.1 TCRCD HCR.0 TFS THR TABT NAME AND DESCRIPTION Not ...
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HSR: HDLC STATUS REGISTER (Address = B1 Hex) (MSB) FRCL RPE SYMBOL POSITION FRCL HSR.7 RPE HSR.6 RPS HSR.5 RHALF HSR.4 RNE HSR.3 THALF HSR.2 TNF HSR.1 TMEND HSR.0 Note: The RPE, RPS, and TMEND bits are latched and are ...
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HIMR: HDLC INTERRUPT MASK REGISTER (Address = B2 Hex) (MSB) FRCL RPE SYMBOL POSITION FRCL HIMR.7 RPE HIMR.6 RPS HIMR.5 RHALF HIMR.4 RNE HIMR.3 THALF HIMR.2 TNF HIMR.1 TMEND HIMR.0 RPS RHALF RNE NAME AND DESCRIPTION Framer Receive Carrier Loss. ...
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RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = B3 Hex) (MSB) RABT RCRCE ROVR SYMBOL POSITION RABT RHIR.7 RCRCE RHIR.6 ROVR RHIR.5 RVM RHIR.4 REMPTY RHIR.3 POK RHIR.2 CBYTE RHIR.1 OBYTE RHIR.0 Note: The RABT, RCRCE, ROVR, and RVM bits are ...
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THIR: TRANSMIT HDLC INFORMATION REGISTER (Address = B6 Hex) (MSB) — — SYMBOL POSITION — THIR.7 — THIR.6 — THIR.5 — THIR.4 — THIR.3 TEMPTY THIR.2 TFULL THIR.1 TUDR THIR.0 Note: The TUDR bit is latched and is cleared when ...
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RDC1: RECEIVE HDLC DS0 CONTROL REGISTER 1 (Address = B8 Hex) (MSB) RHS RSaDS RDS0M SYMBOL POSITION RHS RDC1.7 RSaDS RDC1.6 RDS0M RDC1.5 RD4 RDC1.4 RD3 RDC1.3 RD2 RDC1.2 RD1 RDC1.1 RD0 RDC1.0 RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 ...
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TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address = BA Hex) (MSB) THE TSaDS TDS0M SYMBOL POSITION THE TDC1.7 TSaDS TDC1.6 TDS0M TDC1.5 TD4 TDC1.4 TD3 TDC1.3 TD2 TDC1.2 TD1 TDC1.1 TD0 TDC1.0 TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 ...
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LINE INTERFACE FUNCTIONS The line interface function in the DS21354/DS21554 contains three sections: (1) the receiver, which handles clock and data recovery; (2) the transmitter, which waveshapes and drives the E1 line; and (3) the jitter attenuator. Each of ...
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Receive Clock and Data Recovery 15.1. The DS21354/DS21554 contain a digital clock recovery system. See details. The device couples to the receive-E1-shielded twisted pair or coax via a 1:1 transformer. See Table 15-3 for transformer details. The 2.048MHz clock attached ...
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Table 15-2. Line Build-Out Select in LICR for the DS21354 APPLICATION 75W normal 120W normal 75W with protection resistors 120W with protection resistors 1 0 ...
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Figure 15-1. Basic External Analog Connections E1 Transmit Line E1 Receive Line NOTE 1: ALL CAPACITORS VALUES ARE IN mF. NOTE 2: 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION. NOTE 3: SEE TABLE 15-3 FOR TRANSFORMER SELECTION. Figure 15-2. ...
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Figure 15-3. Jitter Tolerance 1K 100 0.1 1 Figure 15-4. Jitter Attenuation 0dB -20dB -40dB -60dB 1 DS21354/ DS21554 Tolerance 1.5 Minimum Tolerance Level as per ITU G.823 20 10 100 1K FREQUENCY (Hz) ETS 300 011 ...
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Figure 15-5. Transmit Waveform Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 194ns 219ns -150 -100 - TIME (ns 124 269ns G.703 Template 100 150 200 ...
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Protected Interfaces 15.4. In certain applications, such as connecting to the PSTN required that the network interface be protected from and resistant to certain electrical conditions. These conditions are divided into two categories, surge and power line cross. ...
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Figure 15-6. Protected Interface Example for the DS21554 R1 Fuse Transmit R2 Line Fuse R3 Fuse Receive R4 Line Fuse NOTE 1: ALL CAPACITOR VALUES ARE IN mF. NOTE 2: THE 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION. NOTE ...
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Figure 15-7. Protected Interface Example for the DS21354 2:1 Fuse Transmit Line Fuse X1 1:1 Fuse Receive Line Fuse X2 NOTE 1: ALL CAPACITOR VALUES ARE IN mF. NOTE 2: THE 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION. NOTE ...
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Receive Monitor Mode 15.5. When connecting to a monitor port, a large resistive loss is incurred due to the voltage divider between the E1 line termination resistors (Rt) and the monitor port isolation resistors (Rm), as shown in Figure 15-8. ...
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JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS21354/DS21554 SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) TAP Controller Instruction ...
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Figure 16-1. JTAG Functional Block Diagram +V 10kW JTDI BOUNDARY SCAN REGISTER IDENTIFICATION REGISTER BYPASS REGISTER INSTRUCTION REGISTER TEST ACCESS PORT +V +V 10kW 10kW JTRST JTMS JTCLK 91 of 124 SELECT OUTPUT ENABLE JTDO ...
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TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 16-2. Test-Logic-Reset Upon power up, the TAP Controller will be in the ...
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Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the ...
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Figure 16-2. TAP Controller State Diagram Test Logic 1 Reset Run Test/ 0 Idle Select DR-Scan 0 1 Capture DR 0 Shift Exit DR 0 Pause Exit2 DR 1 ...
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Instruction Register 16.1. The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI ...
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JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The ID code will ...
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Table 16-4. Boundary Scan Control Bits BIT PIN NAME TYPE 2 1 RCHBLK O — 2 JTMS 8MCLK O — 4 JTCLK I — 5 JTRST RCL O — 7 JTDI I — 8 ...
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INTERLEAVED PCM BUS OPERATION In many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. The DS21354/DS21554 can be configured to allow data and signaling buses to be multiplexed ...
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Figure 17-1. IBO Basic Configuration Using Four SCTs CI RSYSCLK TSYSCLK RSYNC TSSYNC MASTER RSIG SCT TSIG TSER CO RSER CI RSYSCLK TSYSCLK RSYNC TSSYNC SLAVE #1 RSIG TSIG TSER CO RSER Channel Interleave 17.1. In channel interleave mode data ...
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FUNCTIONAL TIMING DIAGRAMS Receive 18.1. Figure 18-1. Receive-Side Timing 1 FRAM RFSYNC 1 RSYNC 2 RSYNC 3 RLCLK 4 RLINK NOTE 1: RSYNC IN FRAME MODE (RCR1.6 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (RCR1.6 ...
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Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) RSYSCLK CHANNEL 23/31 1 RSER 2 RSYNC RMSYNC 3 RSYNC RCHCLK 4 RCHBLK NOTE 1: DATA FROM THE E1 CHANNELS 13, 17, 21, 25, AND 29 IS ...
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Figure 18-5. Receive-Side Interleave Bus Operation, Byte Mode RSYNC 1 R SER FR1 CH32 1 R SIG FR1 CH32 2 FR2 CH32 FR3 CH32 FR0 CH1 R SER 2 R SIG FR2 CH32 FR3 CH32 FR0 CH1 SYSCLK 3 RSYNC ...
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Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode RSYNC 1 FR1 CH1- FR1 CH1- FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 ...
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Transmit 18.2. Figure 18-7. Transmit-Side Timing FRAME TSYNC TSSYNC 2 TSYNC 3 TLCLK 3 TLINK NOTE 1: TSYNC IN FRAME MODE (TCR1.1 = 0). NOTE 2: TSYNC IN MULTIFRAME MODE (TCR1.1 ...
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Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) TSYSCLK CHANNEL 23 1 TSER TSSYNC TCHCLK 2 TCHBLK NOTE 1: THE F-BIT POSITION IN THE TSER DATA IS IGNORED. NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. Figure ...
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Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode TSYNC 1 TSER FR1 CH32 1 FR1 CH32 TSIG 2 FR2 CH32 FR3 CH32 FR0 CH1 TSER 2 FR2 CH32 FR3 CH32 FR0 CH1 TSIG SYSCLK 3 TSYNC FRAMER 3, CHANNEL 32 ...
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Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode TSYNC 1 FR1 CH1-32 TSER 1 FR1 CH1-32 TSIG 2 TSER FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 2 ...
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Figure 18-13. G.802 Timing ...
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Figure 18-14. DS21354/DS21554 Framer Synchronization Flowchart RLOS = 1 Resync if RCR1 Increment CRC4 Sync Counter; CRC4SA = 0 Set FASRC (RIR.1) CRC4 Resync Criteria Met (RIR.2) CAS Resync Criteria Met; Set CASRC (RIR.0) 8ms CRC4 Multiframe Search ...
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Figure 18-15. DS21354/DS21554 Transmit Data Flow AF.0 Data Source ( TAF TN AF.5-7 0 TAF/ ...
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OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………………-1.0V to +6.0V Operating Temperature Range for DS21354L/DS21554L……………………………………………………0°C to +70°C Operating Temperature Range for DS21354LN/DS21554LN……………………………………………..-40°C to +85°C Storage Temperature Range………………………………………………………………………………...-55°C to +125°C Soldering Temperature………………………………………………………..See IPC/JEDEC J-STD-020A Specification ...
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AC TIMING PARAMETERS AND DIAGRAMS Multiplexed Bus AC Characteristics 20.1. AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT (MUX = 3.3V ± 5 0°C to +70°C; for DS21354L 3.3V ± 5 ...
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Figure 20-1. Intel Bus Read Ac Timing (BTS = 0/MUX = 1) ALE t ASD AD0–AD7 Figure 20-2. Intel Bus Write Timing (BTS = 0/MUX = 1) ALE t ASD AD0–AD7 t CYC ...
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Figure 20-3. Motorola Bus AC Timing (BTS = 1/MUX = ASD R/W AD0–AD7 (READ) CS AD0–AD7 (WRITE) PW ASH t ASED t RWS t DDR t ASL t AHL ASL t ...
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Nonmultiplexed Bus AC Characteristics 20.2. AC CHARACTERISTICS—NONMULTIPLEXED PARALLEL PORT (MUX = 0) = 3.3V ± 5 0°C to +70°C; for DS21354L 3.3V ± 5 -40°C to +85°C for DS21354LN; V ...
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Figure 20-5. Intel Bus Write AC Timing (BTS = 0/MUX = 0) A0–A7 D0– 0ns MIN WR Figure 20-6. Motorola Bus Read AC Timing (BTS = 1/MUX = 0) A0–A7 D0– 0ns MIN DS Figure ...
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Receive-Side AC Characteristics 20.3. AC CHARACTERISTICS—RECEIVE SIDE = 3.3V ± 5 0°C to +70°C; for DS21354L 3.3V ± 5 -40°C to +85°C for DS21354LN (See Figure 20-8 ...
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Figure 20-8. Receive-Side AC Timing RCLK t D1 RSER / RDATA / RSIG RCHCLK RCHBLK RFSYNC / RMSYNC 1 RSYNC 2 RLCLK RLINK Notes: 1. RSYNC is in the output mode (RCR1.5 = 0). 2. RLCLK will only pulse high ...
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Figure 20-9. Receive System Side AC Timing t R RSYSCLK t D3 RSER / RSIG RCHCLK RCHBLK RMSYNC / CO 1 RSYNC 2 RSYNC CI Notes: 1. RSYNC is in the output mode (RCR1 RSYNC is in ...
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Figure 20-10. Receive Line Interface AC Timing RCLKO t DD RPOSO, RNEGO t R RCLKI RPOSI, RNEGI 120 of 124 ...
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Transmit AC Characteristics 20.4. AC CHARACTERISTICS—TRANSMIT SIDE = 3.3V ± 5 0°C to +70°C; for DS21354L 3.3V ± 5 -40°C to +85°C for DS21354LN (See Figure 20-11 ...
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Figure 20-11. Transmit-Side AC Timing t R TCLK TESO TSER / TSIG / TDATA TCHCLK TCHBLK 1 TSYNC 2 TSYNC 5 TLCLK TLINK Notes: 1. TSYNC is in the output mode (TCR1.0 = 1). 2. TSYNC is in the input ...
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Figure 20-12. Transmit System Side AC Timing t R TSYSCLK TSER TCHCLK / CO TCHBLK TSSYNC CI Notes: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and ...
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... Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time © 2004 Maxim Integrated Products · Printed USA 124 of 124 ...