ED DDR3 1G PCF8000 Samsung Semiconductor, ED DDR3 1G PCF8000 Datasheet
ED DDR3 1G PCF8000
Specifications of ED DDR3 1G PCF8000
Related parts for ED DDR3 1G PCF8000
ED DDR3 1G PCF8000 Summary of contents
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... K4B1G04(08/16)46E 1Gb E-die DDR3 SDRAM Specification FBGA with Lead-Free & Halogen-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4B1G04(08/16)46E Revision History Revision Month Year 1.0 February 2009 - First release History Page 1Gb DDR3 SDRAM Rev. 1.0 February 2009 ...
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... Package Pinout (Top view) : 96ball FBGA Package 3.4 FBGA Package Dimension (x4/x8) 3.5 FBGA Package Dimension (x16) 4.0 Input/Output Functional Description ....................................................................................... 11 5.0 DDR3 SDRAM Addressing ........................................................................................................ 12 6.0 Absolute Maximum Ratings ...................................................................................................... 13 6.1 Absolute Maximum DC Ratings 6.2 DRAM Component Operating Temperature Range 7.0 AC & ...
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... K4B1G04(08/16)46E 11.0 1Gb DDR3 SDRAM E-die IDD Specification Table ................................................................ 38 12.0 Input/Output Capacitance ....................................................................................................... 40 13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 .............................. 41 .................................................................................................................. 41 13.1 Clock Specification 13.1.1 Definition for tCK(avg) 13.1.2 Definition for tCK(abs) 13.1.3 Definition for tCH(avg) and tCL(avg) 13.1.4 Definition for note for tJIT(per), tJIT(per, Ick) 13 ...
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... All of Lead-Free products are compliant for RoHS • All of products are Halogen-free Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing Diagram”. DDR3-1066 (7-7-7) ...
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... Top view (See the balls through the package DQ0 DM SSQ DQ2 DQS DQ1 V NC DQS DDQ V RAS CAS A10/AP BA0 BA2 A12/ A11 RESET A13 Page 1Gb DDR3 SDRAM SSQ DDQ V DQ3 C SSQ SSQ DDQ CKE REFCA SS V BA1 Rev. 1.0 February 2009 ...
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... V NC NU/TDOS DD V DQ0 DM/TDQS SSQ DQ2 DQS DQ1 V DQ6 DQS DD V DQ4 DQ7 DDQ V RAS CAS A10/AP BA0 BA2 A12/ A11 RESET A13 Page 1Gb DDR3 SDRAM SSQ DDQ V DQ3 C SSQ SSQ V DQ5 E DDQ CKE REFCA SS V BA1 Rev. 1.0 February 2009 ...
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... DQU0 DDQ V DQL0 DML SSQ DQL2 DQSL DQL1 V DQL6 DQSL DD V DQL4 DQL7 DDQ V RAS CAS A10/AP BA0 BA2 A12/ A11 RESET A13 NC Page 1Gb DDR3 SDRAM DDQ SS V DQU6 B SSQ V DQU2 C DDQ SSQ SSQ DDQ V DQL3 F SSQ SSQ V DQL5 H DDQ ...
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... Reflow ∅0.50 ± 0.05) 0 #A1 7.50 ± 0.10 A #A1 INDEX MARK 0.80 1.60 3. (0.95) MOLDING AREA (1.90) BOTTOM VIEW 7.50 ± 0.10 TOP VIEW Page 1Gb DDR3 SDRAM Units : Millimeters B 0.35 ± 0.05 1.10 ± 0.10 Rev. 1.0 February 2009 ...
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... Reflow ∅0.50 ± 0.05) 0 #A1 7.50 ± 0.10 A #A1 INDEX MARK 0.80 1.60 3. (0.95) MOLDING AREA (1.90) BOTTOM VIEW 7.50 ± 0.10 TOP VIEW Page 1Gb DDR3 SDRAM Units : Millimeters B 0.35 ± 0.05 1.10 ± 0.10 Rev. 1.0 February 2009 ...
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... Input/Output strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide dif- ferential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS ...
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... K4B1G04(08/16)46E 5.0 DDR3 SDRAM Addressing 1Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly *1 Page size 2Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address BC switch on the fly *1 Page size 4Gb Configuration # of Bank Bank Address ...
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... Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. ...
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... Min. Max 100 V REF 100 SS REF V + 175 - REF V - 175 - REF 0.49*V 0.51 (DC) REFDQ to deviate from V (DC) by more than REF REF Page 1Gb DDR3 SDRAM DDR3-1333/1600 Min. Max 100 V REF 100 SS REF V + 175 - REF V - 175 - REF V +150 - REF V -150 - REF 0.49*V 0.51*V ...
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... System timing and voltage budgets need to account for V data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V and voltage effects due to ac-noise on V REF ...
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... DQS - DQS, DQSL - DQSL, DQSU - DQSU use V REFCA tDVAC [ps (AC)| = 350mV IH/Ldiff min max Page 1Gb DDR3 SDRAM tDVAC time unit max note 3 V -0.2 V note (AC)) V REF IL /V (AC) of DQs and REFDQ tDVAC [ps (AC)| = 300mV IH/Ldiff min max 175 ...
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... SEL SEH DDR3-800/1066/1333/1600 Min (V /2)+0.175 DD (V /2)+0.175 DD Note3 Note3 ; V (AC)/V (AC) for ADD/CMD is based Page 1Gb DDR3 SDRAM (AC (AC)} for ADD/CMD signals] in every IH IL (AC (AC)} for DQ signals] in every half-cycle IH IL 150(AC)/V 150(AC) is used for ADD/CMD sig DQS V SEL time Unit ...
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... Figure 4. V Definition IX /2 for CK, for DQS,DQS DD (DC)min and the first crossing Measured From V V ILdiffmax V V IHdiffmin delta TFdiff delta TRdiff Page 1Gb DDR3 SDRAM is measured from the actual CK, DQS CK, DQS V SS DDR3-800/1066/1333/1600 Unit Min Max -150 150 -175 175 ...
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... From To V (AC) V (AC (AC) V (AC DDR3-800 DDR3-1066 Min Max Min Max 2.5 5 2.5 5 TFse TRse delta delta Figure 6. Single-ended Output Slew Rate Definition Page 1Gb DDR3 SDRAM DDR3-800/1066/1333/1600 Units 0 DDQ 0 DDQ 0 DDQ DDQ DDQ DDR3-800/1066/1333/1600 Units +0 DDQ -0 DDQ (AC) and V ...
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... Min Max TFdiff TRdiff delta delta Figure 7. Differential Output Slew Rate Definition V DDQ DQ DUT DQS DQS Reference Point Page 1Gb DDR3 SDRAM OLdiff Defined by V (AC)-V (AC) OHdiff OLdiff Delta TRdiff V (AC)-V (AC) OHdiff OLdiff Delta TFdiff DDR3-1333 DDR3-1600 Min Max Min ...
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... Specification DDR3-800 DDR3-1066 0.4V 0.4V 0.4V 0.4V 0.25V-ns 0.19V-ns 0.25V-ns 0.19V-ns Maximum Amplitude Overshoot Area Undershoot Area Maximum Amplitude Time (ns) Page 1Gb DDR3 SDRAM Unit DDR3-1333 DDR3-1600 0.4V 0.4V V 0.4V 0.4V V 0.4V-ns 0.33V-ns V-ns 0.4V-ns 0.33V-ns V-ns Overshoot Area Undershoot Area ...
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... V 0.9 OMdc DDQ 0.6 OHdc DDQ -10 OMdc DDQ = V and that DDQ DD SSQ SS DDQ DDQ Page 1Gb DDR3 SDRAM V DDQ DQ Iout Vout V SSQ Nom Max Units 1.0 1.1 1.0 1.1 1.0 1.4 RZQ/7 1.0 1.4 1.0 1.1 1.0 1.1 1 ...
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... Chip in Termination Mode ODT Ipu To RTT other Pu circuitry like RCV, RTT ... Pd Ipd Page 1Gb DDR3 SDRAM Max dTH * | ∆ dVH * |∆ dTM * | ∆ dVM * |∆ dTL * | ∆ dVL * |∆ 1600 Min Max 0 1.5 0 0. ...
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... RTT 0.5XV 60pd240 DDQ V (DC) 0.8XV OH DDQ V (DC) 0.2XV OL DDQ RTT 0.5XV 60pu240 DDQ V (DC) 0.8XV OH DDQ RTT V (AC (AC Page 1Gb DDR3 SDRAM RTT RTT RTT 60pd120, 60pu120, 120pd240, 120pu240, Min Nom Max Unit R 0.6 1.0 1 0.9 1.0 1 0.9 1.0 1 0.9 1 ...
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... ∆ DDQ (@calibration DDQ Min 0 ∆ |∆ Min 0 0 Page 1Gb DDR3 SDRAM = Other calibration schemes may be used to achieve the linearity (AC)) perspectively IL (AC)) x 100 Max 1 ∆ |∆ Max 1.5 0.15 Rev. 1.0 February 2009 Units RZQ/2,4,6,8,12 Units %/°C %/mV ...
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... RTT_Wr Setting V [V] SW1 NA 0.05 NA 0.10 NA 0.05 NA 0.10 NA 0.05 NA 0.10 NA 0. 0.20 ZQ Page 1Gb DDR3 SDRAM RTT SSQ =25 ohm End Point Definition SSQ SSQ RTT_Nom RTT_Nom and V RTT_Wr RTT_Nom V [V] Note SW2 0.10 0.20 0.10 0.20 0.10 0.20 0.10 ...
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... Figure 14. Definition of tAON t AONPD T SW2 T SW1 V SW2 V SW1 End point Extrapolated point at V SSQ Figure 15. Definition of tAONPD t AOF End point Extrapolated point at V RTT_Nom T SW2 T SW1 SW1 Figure 16. Definition of tAOF Page 1Gb DDR3 SDRAM SSQ SSQ SSQ TD_TAON_DEF Rev. 1.0 February 2009 ...
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... Begin point : Rising edge defined by the end point of ODTLcwn4 or ODTLcwn8 t ADC End point Extrapolated point at V RTT_Nom T SW21 V SW2 T SW11 V SW1 V RTT_Wr Figure 18. Definition of tADC Page 1Gb DDR3 SDRAM SSQ ADC V RTT_Nom T SW22 T SW12 End point Extrapolated point at V RTT_Wr V SSQ ...
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... IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all V together. Any IDD current is not included in IDDQ currents. Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since V are using one merged-power layer in Module PCB ...
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... Number Figure 20. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement. (optional) I DDQ V DDQ DQS, DQS DQ, DM, TDQS, TDQS V SSQ IDDQ Simulation Correction Page 1Gb DDR3 SDRAM Ohm DDQ IDDQ Test Load IDDQ Measurement Correlation Rev. 1.0 February 2009 ...
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... AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially tog AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: partially d) ; Self-Refresh Temperature Range (SRT): Normal b) ; ODT Signal: MID-LEVEL Page 1Gb DDR3 SDRAM b) ; ODT b) ; ODT b) ; ODT Signal: stable at 0; Precharge b) ; ODT Signal: stable at 0; Precharge b) ...
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... Auto Self-Refresh (ASR): set MR2 disable enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device g) Read Burst type : Nibble Sequential, set MR0 A[3]=0B ...
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... Sub-Loop 0, use BA[2: instead 6 12*nRC repeat Sub-Loop 0, use BA[2: instead 7 14*nRC repeat Sub-Loop 0, use BA[2: instead Note : 1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL signals are MID-LEVEL Page 1Gb DDR3 SDRAM Rev. 1.0 February 2009 - - - - - - - ...
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... Sub-Loop 0, use BA[2: instead 6 24-27 repeat Sub-Loop 0, use BA[2: instead 7 28-31 repeat Sub-Loop 0, use BA[2: instead Note : 1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL signals are MID-LEVEL Page 1Gb DDR3 SDRAM Rev. 1.0 February 2009 - - - ...
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... Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL D D Page 1Gb DDR3 SDRAM Rev. 1.0 February 2009 - 00000000 - - 00110011 ...
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... BA[2: 33...nRFC - 1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary. Note : 1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL signals are MID-LEVEL Page 1Gb DDR3 SDRAM Rev. 1.0 February 2009 00000000 - - 00110011 - - - - - ...
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... Assert and repeat above D Command until 4*nFAW - 1, if necessary Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL Page 1Gb DDR3 SDRAM ...
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... K4B1G04(08/16)46E 11.0 1Gb DDR3 SDRAM E-die IDD Specification Table [ Table 40 ] IDD Specification for 1Gb DDR3 E-die Symbol DDR3-800 6-6-6 IDD0 55 IDD1 70 IDD2P0(slow exit) 10 IDD2P1(fast exit) 25 IDD2N 30 IDD2NT 30 IDD2Q 25 IDD3P(fast exit) 25 IDD3N 40 IDD4R 85 IDD4W 85 IDD5B 150 IDD6 10 IDD7 170 Symbol DDR3-800 6-6-6 ...
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... DDR3-1066 DDR3-1333 7-7-7 9-9 130 160 130 155 150 160 10 10 200 240 Page 1Gb DDR3 SDRAM DDR3-1600 Unit Notes TBD TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA TBD mA Rev. 1.0 February 2009 ...
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... CDIO -0.5 0.3 -0.5 CZQ - applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). SSQ Page 1Gb DDR3 SDRAM DDR3-1333 DDR3-1600 Max Min Max Min Max 2.7 1.5 2.5 1.5 2.3 1.6 ...
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... Definition for tERR(nper) tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test. N=200 N ∑ tCLj N=200 j=1 Page 1Gb DDR3 SDRAM N x tCK(avg) N=200 Rev. 1.0 February 2009 ...
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... Average periodic refresh interval Note : 1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. 13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin ...
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... Reserved tCK(AVG) Reserved 1.875 tCK(AVG) (Optional) Note 5,9 tCK(AVG) Reserved tCK(AVG) Reserved tCK(AVG) 1.875 tCK(AVG) Reserved tCK(AVG) Reserved tCK(AVG) 1.5 tCK(AVG) Reserved 1.5 tCK(AVG) (Optional) 6,7,8,9 5,6,7 Page 1Gb DDR3 SDRAM Units Note max 9*tREFI ns 8 3.3 ns 1,2,3,7 ns 1,2,3,4 <2.5 ns 1,2,3,4,7 ...
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... Reserved tCK(AVG) Reserved tCK(AVG) Reserved 1.5 tCK(AVG) (Optional) Note 9,10 tCK(AVG) TBD tCK(AVG) Reserved 1.5 tCK(AVG) (Optional) Note 9,10 tCK(AVG) Reserved tCK(AVG) Reserved tCK(AVG) 1.25 6,7,8,9,10,11 5,6,7,8 Page 1Gb DDR3 SDRAM Units Note max 9*tREFI ns 3.3 ns 1,2,3,8 ns 1,2,3,4 <2.5 ns 1,2,3,4,8 ...
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... SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and 48.125ns (tRAS- min+tRPmin=35ns+13.125ns) for DDR3-1600(CL11). = 1.5V +/- 0.075 V); Page 1Gb DDR3 SDRAM Rev. 1.0 February 2009 ...
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... Page 1Gb DDR3 SDRAM DDR3-1333 DDR3-1600 MAX MIN MAX MIN MAX - tCK(avg)min + tCK(avg)max + tCK(avg)min + tCK(avg)max + tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max 0.53 0.47 0.53 ...
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... FC + 10ns 10ns) tXSDLL tDLLK(min) - tDLLK(min) tCKE(min) + tCKE(min) + tCKESR - 1tCK 1tCK max(5nCK, max(5nCK, tCKSRE - 10ns) 10ns) max(5nCK, max(5nCK, tCKSRX - 10ns) 10ns) Page 1Gb DDR3 SDRAM DDR3-1333 DDR3-1600 MAX MIN MAX MIN MAX - 512 - 512 max max - - (4nCK,7.5ns) (4nCK,7.5ns) max max - - (4nCK,7.5ns) (4nCK,7.5ns) - ...
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... Page 1Gb DDR3 SDRAM DDR3-1333 DDR3-1600 MAX MIN MAX MIN MAX max max - - - (3nCK,6ns) (3nCK,6ns) max max - (10nCK, - (10nCK, - 24ns) 24ns) max max - (3nCK (3nCK,5ns) 5 ...
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... Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 593 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 572 ps ...
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... The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See Device Operation. 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD 13 ...
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... Page 1Gb DDR3 SDRAM (DC)max and the first crossing (DC)min and the first crossing (DC) region’, use nominal slew rate for derating value (see REF (DC) region’, the slew rate of a tangent line REF (AC) at the time of the rising clock ...
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... V (AC)} for valid transition @175mV [ps] VAC min max Page 1Gb DDR3 SDRAM (AC (DC) - 150mV IL REF 1.6 V/ns 1.4V/ns 1.2V/ns ∆tIH ∆tIS ∆tIH ∆tIS ∆tIH 107 - - -44 -1 -36 7 -26 t @150mV [ps] ...
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... REF region nominal slew rate tVAC Delta TF Delta TR Setup Slew Rate V (DC (AC)max REF IL = Rising Signal Delta TF Page 1Gb DDR3 SDRAM tIS tIH tDH tDS tVAC nominal slew rate REF region V (AC)min - V (DC) IH REF = Delta TR Rev. 1.0 February 2009 ...
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... V REF region nominal REF slew rate region Delta TR V (DC (DC)max Hold Slew Rate REF IL = Delta TR Falling Signal Page 1Gb DDR3 SDRAM tIH tIS tDH tDS nominal slew rate REF region Delta TF V (DC)min - V (DC) IH REF = Delta TF Rev. 1.0 February 2009 ...
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... REF region tangent line line Delta TR Setup Slew Rate = Rising Signal Delta TF tangent line[V (DC (AC)max] REF IL = Delta TF Page 1Gb DDR3 SDRAM tIH tIS tDH tDS tVAC tangent line REF region tangent line[V (AC)min - V (DC)] IH REF Delta TR Rev. 1.0 February 2009 ...
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... REF region tangent line REF region nominal line Delta TR (DC (DC)max ] REF IL = Delta TR tangent line [ V Hold Slew Rate = Falling Signal Page 1Gb DDR3 SDRAM tIH tIS tDS tDH nominal line tangent line Delta TF (DC)min - V (DC REF Delta TF Rev. 1.0 February 2009 ...
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... Page 1Gb DDR3 SDRAM (DC) and the first crossing of V REF (DC) and the first crossing of V REF (DC region’, use nominal slew rate for REF (DC)max and the first crossing (DC)min and the first crossing (DC) region’, use nominal slew rate REF (DC) region’ ...
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... REF region nominal slew rate tVAC Delta TF Delta TR Setup Slew Rate V (DC (AC)max REF IL = Rising Signal Delta TF Page 1Gb DDR3 SDRAM tIS tIH tDH tDS tVAC nominal slew rate REF region V (AC)min - V (DC) IH REF = Delta TR Rev. 1.0 February 2009 ...
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... V REF region nominal REF slew rate region Delta TR V (DC (DC)max Hold Slew Rate REF IL = Falling Signal Delta TR Page 1Gb DDR3 SDRAM tIH tIS tDH tDS nominal slew rate REF region Delta TF V (DC)min - V (DC) IH REF = Delta TF Rev. 1.0 February 2009 ...
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... REF region tangent line line Delta TR Setup Slew Rate = Rising Signal Delta TF tangent line[V (DC (AC)max] REF IL = Delta TF Page 1Gb DDR3 SDRAM tIH tIS tDH tDS tVAC tangent line REF region tangent line[V (AC)min - V (DC)] IH REF Delta TR Rev. 1.0 February 2009 ...
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... REF region tangent line REF region nominal line Delta TR (DC (DC)max ] REF IL = Delta TR tangent line [ V Hold Slew Rate = Falling Signal Page 1Gb DDR3 SDRAM tIH tIS tDS tDH nominal line tangent line Delta TF (DC)min - V (DC REF Delta TF Rev. 1.0 February 2009 ...