SI3019-F-FT Silicon Laboratories Inc, SI3019-F-FT Datasheet - Page 110

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SI3019-F-FT

Manufacturer Part Number
SI3019-F-FT
Description
IC VOICE DAA GCI/PCM/SPI 16TSSOP
Manufacturer
Silicon Laboratories Inc
Type
Chipsetr
Datasheets

Specifications of SI3019-F-FT

Package / Case
16-TSSOP
Function
Data Access Arrangement (DAA)
Interface
GCI, PCM, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Product
Modem Chip
Supply Voltage (min)
3 V
Supply Current
8.5 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI3019-F-FTR
Manufacturer:
SiliconL
Quantity:
5 000
Part Number:
SI3019-F-FTR
Manufacturer:
SiliconLa
Quantity:
872
Part Number:
SI3019-F-FTR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Si3050
D
Revision 1.01 to Revision 1.1
Revision 1.1 to Revision 1.2
110
OCUMENT
Added package thermal information in Table 1,
“Recommended Operating Conditions and Thermal
Information,” on page 5.
Added Note 10 to the transhybrid balance parameter
in Table 4 on page 8.
Updated Table 7, “Switching Characteristics—Serial
Peripheral Interface,” on page 11.
Removed R54 and R55 from "3. Bill of Materials" on
page 18.
Changed recommended DCV setting for Japan from
01 to 10 in Table 13 on page 21.
Updated initialization procedure in "5.3. Initialization"
on page 24.
Removed incorrect description of FDT bit in "5.8.
Exception Handling" on page 26.
Updated Billing Tone and Receive Overload section.
Changed to "5.22. Receive Overload Detection" on
page 33.
Updated text and added description of hybrid
coefficient format in "5.28. Transhybrid Balance" on
page 37.
Removed references to line-side revisions C and E.
Updated "9. Ordering Guide" on page 102.
Updated package information for 20-Pin TSSOP and
16-Pin SOIC on pages 103 and 104.
Added "13. Package Outline: 16-Pin TSSOP" on
page 107.
Updated Table 7, “Switching Characteristics—Serial
Peripheral Interface,” on page 11.
Updated Table 13, “Country Specific Register
Settings,” on page 21.
Updated "5.3. Initialization" on page 24.
Updated Figure 25, “Si3018/19 Signal Flow
Diagram,” on page 37.
Updated "9. Ordering Guide" on page 102.
Updated delay time between chip selects.
Corrected ACIM settings for Brazil.
Revised Step 6 with standard hexadecimal notation.
Corrected HPF pole.
C
HANGE
L
IST
Rev. 1.2

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