SI3019-F-FT Silicon Laboratories Inc, SI3019-F-FT Datasheet - Page 86

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SI3019-F-FT

Manufacturer Part Number
SI3019-F-FT
Description
IC VOICE DAA GCI/PCM/SPI 16TSSOP
Manufacturer
Silicon Laboratories Inc
Type
Chipsetr
Datasheets

Specifications of SI3019-F-FT

Package / Case
16-TSSOP
Function
Data Access Arrangement (DAA)
Interface
GCI, PCM, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Product
Modem Chip
Supply Voltage (min)
3 V
Supply Current
8.5 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Si3050
Register 37. PCM Receive Start Count—High Byte
Reset settings = 0000_0000
Register 38. TX Gain Control 2
Reset settings = 0000_0000
86
Bit
7:2
1:0
Bit
7:5
3:0
4
Name
Name
Type
Type
Bit
Bit
TXG2[3:0] Transmit Gain 2.
Reserved Read returns zero.
Reserved
Name
RXS[1:0]
TGA2
Name
D7
D7
Transmit Gain or Attenuation 2.
0 = Incrementing the TXG2[3:0] bits results in gaining up the transmit path.
1 = Incrementing the TXG2[3:0] bits results in attenuating the transmit path.
Each bit increment represents 1 dB of gain or attenuation, up to a maximum of +12 dB and
–15 dB respectively.
For example:
TGA2
X
0
0
0
1
1
1
PCM Receive Start Count.
PCM Receive Start Count equals the number of PCLKs following FSYNC before data
reception begins.
Read returns zero.
D6
D6
TXG2[3:0]
0000
0001
11xx
0001
1111
:
:
D5
D5
0 dB gain or attenuation is applied to the transmit path.
1 dB gain is applied to the transmit path.
12 dB gain is applied to the transmit path.
1 dB attenuation is applied to the transmit path.
15 dB attenuation is applied to the transmit path.
Result
Rev. 1.2
TGA2
R/W
D4
D4
Function
Function
D3
D3
D2
D2
TXG2[3:0]
R/W
D1
D1
RXS[1:0]
R/W
D0
D0

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