SI3063-F-FS Silicon Laboratories Inc, SI3063-F-FS Datasheet
SI3063-F-FS
Specifications of SI3063-F-FS
Related parts for SI3063-F-FS
SI3063-F-FS Summary of contents
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Features Complete DAA includes the following dynamic range TX/RX paths to support up to V.92 modem speeds Programmable line interface AC termination DC termination ...
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... Si306x 1. Si306x Selection Guide System-Side Part Number Requirement Si3060-X-FS Si3061-X-FS For use with integrated Si3062-X-FS system-side module only Si3063-X-FS Si3065-X-FS 2 Description Region Terminations FCC Line-side FCC Global Line-side Global Enhanced FCC FCC Line-side Enhanced Global Global Line-side Enhanced FCC/ FCC/TBR21 TBR21 Line-side Rev ...
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Section 1. Si306x Selection Guide . . . . . . . . . . . . . . . . . . . . . ...
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Si306x 2. Electrical Specifications Table 1. Recommended Operating Conditions 1 Parameter Ambient Temperature Notes: 1. The Si306x specifications are guaranteed when the typical application circuit (including component tolerance) and any system-side module and any Si306x are used. 2. All minimum ...
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Table 2. Loop Characteristics (V = 3 °C for F/K-Grade Parameter Symbol DC Termination Voltage V DC Termination Voltage V DC Termination Voltage V DC Termination Voltage V DC Termination ...
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Si306x Table 3. DC Characteristics 3 ° Parameter Input Leakage Current * Power Supply Current, Analog *Note: This current is required from the integrated system-side interface to ...
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Table 4. AC Characteristics (V = 3 °C for F/K-Grade, see D A Parameter Sample Rate Transmit Frequency Response Receive Frequency Response Receive Frequency Response 2 Transmit Full Scale Level 2,3 Receive ...
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Si306x Table 5. Absolute Maximum Ratings Parameter Operating Temperature Range Storage Temperature Range Note: Permanent device damage can occur if the above Absolute Maximum Ratings are exceeded. Restrict functional operation to the conditions as specified in the operational sections of ...
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Typical Application Schematic Rev. 0.9 Si306x 9 ...
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Si306x 4. Bill of Materials Component( pF, Y2, X7R, ±20 nF, 250 V, X7R, ±20% C4 1.0 µ Elec/Tant, ±20% C5, C6 0.1 µ X7R, ±20% C7 2.7 nF, 50 ...
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AOUT PWM Output Figure 3 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si306x for call progress monitoring purposes. To enable this mode, the INTE bit (Register 2) should be set to ...
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... Si3060 and Si3062: Single ac termination to meet FCC PTT specifications. Si3065: Two ac termination settings to meet FCC and TBR21 PTT specifications. PTT Si3061 and Si3063: Four ac termination settings to meet global PTT specifications. The Si3062, Si3063, and Si3065 enhanced line-side energy, emissions, devices additionally provide line voltage monitoring and finer resolution loop current monitoring capabilities ...
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... Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. 2. Supported for loop current ≥ 20 mA. 3. Available with Si3061, Si3063, and Si3065 line-sides only. See "6.15. AC Termination" on page 21. 4. See "6.14. DC Termination" on page 20 for DCV and MINI settings. 16 ...
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... Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. 2. Supported for loop current ≥ 20 mA. 3. Available with Si3061, Si3063, and Si3065 line-sides only. See "6.15. AC Termination" on page 21. 4. See "6.14. DC Termination" on page 20 for DCV and MINI settings. 14 ...
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... Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. 2. Supported for loop current ≥ 20 mA. 3. Available with Si3061, Si3063, and Si3065 line-sides only. See "6.15. AC Termination" on page 21. 4. See "6.14. DC Termination" on page 20 for DCV and MINI settings. 16 ...
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Si306x 6.2. Power Supplies The Si306x line-side device derives its power from two sources: The system-side module and the telephone line. The integrated system-side module supplies power over the patented capacitive isolation link between the two devices, allowing the line-side ...
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Calibration The DAA initiates two auto-calibrations by default when the device goes off-hook or experiences a loss in line power resistor calibration is performed to allow circuitry internal to the DAA to adjust to the exact ...
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... DODM bit is set) indicating that the line-derived power supply has collapsed. If the Si3062 or Si3063 line-side device is used, the LVS bits also can be read when on- or off-hook to determine the line voltage. Significant drops in line voltage can signal a parallel handset ...
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... Detection" on page 26). 6.11.1. Line Voltage Measurement (Si3062, Si3063, and Si3065 Only) The Si3062, Si3063, and Si3065 devices report line voltage with the LVS[7:0] bits (Register 29) in both on- and off-hook states with a resolution per bit. The accuracy of these bits is approximately ±10%. Bits 0 through 6 of this register indicate the value of the line voltage in 2s compliment format ...
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... CVT[7:0] bits, and thus only positive numbers should be used as a threshold. This line current/voltage threshold interrupt is only available with the Si3063 and Si3064 line-side devices. 6.14. DC Termination The DAA has programmable settings for dc impedance, minimum operational loop current, and TIP/RING voltage ...
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... With the Si3060 and Si3062 line-side devices, the ACT bits (Register 16) are forced to zero to provide the necessary 600 Ω termination to satisfy FCC Part 68. With the Si3061 and Si3063, The ACT and ACT2 bits can be programmed to provide three ac impedance selections in addition to the real, nominal 600 Ω ...
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Si306x designed to satisfy minimum return loss requirements for every country in the world that requires a complex termination. For any of the ac termination settings, the programmable digital hybrid can be used to further reduce near-end echo. See the ...
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Ring validation can be enabled during normal operation and in low power sleep mode. The external MCLK signal is required in low power sleep mode for ring validation. The ring validation circuit operates by calculating the time between alternating ...
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Si306x line data. The DAA can provide feedback indicating the beginning and end of a billing tone. Billing tone detection is enabled with the BTE bit (Register 17, bit 2). Billing tones less than 1.1 V the line are filtered ...
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... SDO pin. 4. Clear the ONHM bit after the caller ID data is received. 6.24.2. Type II Caller ID (Si3063 and Si3064 Line-Side Devices Only) Type II Caller ID sends the CID data while the phone is off-hook and is often referred to as caller ID/call waiting (CID/CW) ...
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Si306x 3. The CO then responds with the CID data. After receiving the CID data, the host processor unmutes the upstream data output and continues with normal operation. 4. The muting of the upstream data path by the host processor ...
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To Embedded Link System-Side DAA Module Figure 9. Si306x Signal Flow Diagram SDI IIRE SDO Digital Filter 1 Notes: 1. Available with 32.768 MHz embedded system-side DAA module only. 2. Available with Si3064 line-side device. Figure 10. Embedded System-Side DAA ...
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... Line Current/Voltage Threshold Interrupt Control 45–58 Reserved 59 Spark Quenching Control Notes: 1. Bit is available for Si3062, Si3063, and Si3064 line-side devices only. 2. Bit is available for Si3061 and Si3063 line-side devices only. 3. Bit is available with 32.768 MHz system-side module only. 28 Table 12. Register Summary Bit 7 Bit 6 ...
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Register 1. Control 1 Bit Name SR PWMM[1:0] Type R/W Reset settings = 0000_0000 Bit Name 7 SR Software Reset Enables the DAA for normal operation Sets all registers to their reset value. ...
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Si306x Register 2. Control 2 Bit Name INTE INTP Type R/W R/W Reset settings = 0000_0011 Bit Name 7 INTE Interrupt Pin Enable The INT port is disabled The INT port is enabled. ...
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... Reserved Read returns zero. 0 POLM Polarity Reversal Detect Mask (Si3062, Si3063, and Si3065 line-side devices only). Generated from bit 7 of the LVS register. When this bit transitions, it indicates that the polarity of TIP and RING was switched polarity change on TIP and RING does not cause an interrupt on the INT port. ...
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... Reserved Read returns zero. 0 POLI Polarity Reversal Detect Interrupt (Si3062, Si3063, and Si3065 line-side devices only Bit 7 of the LVS register does not change states Bit 7 of the LVS register changes from from indicating the polarity of TIP and RING is switched. If the POLM and INTE bits are set, a hardware interrupt occurs on the INT port ...
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Register 5. DAA Control 1 Bit Name RDTN RDTP Type R R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 RDTN Ring Detect Signal Negative negative ring signal is occurring. ...
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Si306x Register 6. DAA Control 2 Bit Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 PDL Powerdown Line-Side Device Normal operation. Program the clock generator before clearing this bit. ...
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Register 7. Sample Rate Control Bit Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3:0 SRC[3:0] Sample Rate Control. Sets the sample rate of the line-side device. The following sample rate settings ...
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Si306x Register 8-9. Reserved Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 10. DAA Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved ...
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... LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values depending on which line-side device is used. LSID[3:0] Si3060 Si3061 Si3062 Si3063 Si3064 Si3065 3:0 REVA[3:0] System-Side Revision. Four-bit value indicating the revision of the system-side device. Register 12. Line-Side Device Status ...
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Si306x Register 13. Line-Side Device Revision Bit Name 1 Type Reset settings = xxxx_xxxx Bit Name 7 Reserved Read returns zero This bit always reads a one. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit value indicating ...
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Register 15. TX/RX Gain Control 1 Bit Name TXM ATX[2:0] Type R/W R/W Reset settings = 0000_0000 Bit Name 7 TXM Transmit Mute Transmit signal is not muted Mutes the transmit signal. 6:4 ...
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... This bit, in combination with the OHS2 bit and the SQ[1:0] bits, sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero. Si3061 and Si3063 Settings: OHS OHS2 ...
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... Bit Name 3:2 Reserved Read returns zero Ringer Impedance. Si3061 and Si3063 Settings Maximum (high) ringer impedance Synthesized ringer impedance. See "6.19. Ringer Impedance and Threshold" on page 23. Si3060, Si3062, and Si3065 Settings Maximum (high) ringer impedance Ringer Threshold Select. This bit is used to satisfy country requirements on ring detection. Signals below the lower level do not generate a ring detection ...
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Si306x Register 17. International Control 2 Bit Name CALZ MCAL CALD Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 CALZ Clear ADC Calibration Normal operation Clears the existing calibration data. ...
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Register 18. International Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero or one. 1 RFWE Ring Detector Full Wave Rectifier Enable. When RNGV (Register 24) is disabled, this bit ...
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Si306x Register 19. International Control 4 Bit Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 OVL Receive Overload Detect. This bit has the same function as ROV in Register 17, but ...
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Register 20. Call Progress RX Attenuation Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal used ...
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Si306x Register 22. Ring Validation Control 1 Bit Name RDLY[1:0] Type R/W Reset settings = 1001_0110 Bit Name 7:6 RDLY[1:0] Ring Delay Bits 1 and 0. These bits, in combination with the RDLY[2] bit (Register 23), set ...
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Register 23. Ring Validation Control 2 Bit Name RDLY[2] RTO[3:0] Type R/W Reset settings = 0010_1101 Bit Name 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), set the amount ...
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Si306x Register 24. Ring Validation Control 3 Bit Name RNGV Type R/W Reset settings = 0001_1001 Bit Name 7 RNGV Ring Validation Enable Ring validation feature is disabled Ring validation feature is enabled ...
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Register 25. Resistor Calibration Bit Name RCALS RCALM RCALD Type R R/W R/W Reset settings = xxxx_xxxx Bit Name 7 RCALS Resistor Auto Calibration Resistor calibration is not in progress Resistor calibration is ...
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... Reserved Do not write to these register bits. 1 ILIM Current Limiting Enable. Si3061, Si3063, and Si3065 settings Current limiting mode disabled Current limiting mode enabled. Limits loop current to a maximum per the TBR21 standard. Si3060 and Si3062 settings Current limiting mode disabled. ...
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... Reset settings = 0000_0000 Bit Name 7:0 LCS2[7:0] Loop Current Status. Eight-bit value returning the loop current. Each bit represents 1 loop current. 0000_0000 = Loop current is less than required for normal operation. Register 29. Line Voltage Status (Si3063 and Si3064 Line-Side Device Only) Bit Name Type ...
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... The receive path has a low –3 dBFS corner at 200 Hz. 0 LVFD Line Voltage Force Disable (Si3062, Si3063, and Si3065 Line-Side Devices Only Normal operation The circuitry that forces the LVS register (Register 29) to all less is disabled. The LVS register may display unpredictable values at voltages between All 0s are displayed if the line voltage ...
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... Register 32-42. Reserved Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 43. Line Current / Voltage Threshold Interrupt (Si3062, Si3063, and Si3065 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 CVT[7:0] Current/Voltage Threshold. ...
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... Si306x Register 44. Line Current/Voltage Threshold Interrupt Control (Si3062, Si3063, and Si3065 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 CVI Current/Voltage Interrupt The current / voltage threshold has not been crossed The current / voltage threshold is crossed. If the CVM and INTE bits are set, a hardware interrupt occurs on the INT port ...
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... This bit, in combination with the OHS bit (Register 16), and the OHS2 bit (Register 31), sets the amount of time for the line-side device to go on-hook. The on-hook speeds specified are measured from the time the OH bit is cleared until loop current equals zero. Si3061 and Si3063 settings: OHS OHS2 ...
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Si306x A —UL1950 3 PPENDIX RD Although designs using the Si306x comply with UL1950 3rd Edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 11 shows two designs that can pass the UL1950 ...
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Pin Descriptions: Si306x Pin # Pin Name 1 QE Transistor Emitter. Connects to the emitter of Q3. 2 DCT DC Termination. Provides dc termination to the telephone network Receive Input. Serves as the receive side input from ...
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Si306x Table 13. Si306x Pin Descriptions (Continued) Pin # Pin Name 13 QB Transistor Base. Connects to the base of transistor Q4. 14 DCT3 DC Termination 3. Provides dc termination to the telephone network. 15 IGND Isolated Ground. Connects to ...
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... Si3060-X-ZSR Product Designator Product Revision Line-Side Part Region Number FCC Si3060-X-FS Global Si3061-X-FS Enhanced FCC Si3062-X-FS Enhanced Global Si3063-X-FS Enhanced Global Voice Si3064-X-FS Shipping Option Blank = Tubes R = Tape and Reel Package Type S = SOIC T = TSSOP Part Type/Lead Finish K = Commercial/SnPb X = Customer-specific/SnPb F = Commercial/Lead-Free Z = Customer-specific/Lead-Free Rev ...
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Si306x 11. Package Outline: 16-Pin SOIC Figure 12 illustrates the package details for the Si306x. Table 14 lists the values for the dimensions shown in the illustration aaa - Seating ...
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OCUMENT HANGE IST Revision 0.1 to Revision 0.9 Updated Figure 3 on page 11. Updated Table 2 on page 5. Updated Table 4 on page 7. Updated Table 6 on page 11. Updated Table 7 on page ...
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