M-8870-01SM Clare, M-8870-01SM Datasheet - Page 4

• Manufacturer Part Number: M-8870-01SM
• Description: IC RECEIVER DTMF CMOS LP 18-SOIC
• Manufacturer: Clare

Specifications of M-8870-01SM

• Function: DTMF Receiver
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 3mA
• Power (watts): 35mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Decoder, Dial Tone Suppression
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -

M-8870
4
Guard Time Adjustment
Where independent selection of signal duration and
interdigit pause are not required, the simple steering
circuit of Basic Steering Circuit is applicable.
Component values are chosen according to the formu-
la:
The value of tDP is a parameter of the device and
tREC is the minimum signal duration to be recognized
by the receiver. A value for C of 0.1 µF is recommend-
ed for most applications, leaving R to be selected by
the designer. For example, a suitable value of R for a
t
this steering configuration is shown in the Single -
Ended Input Configuration on page 4. The timing
requirements for most telecommunication applications
are satisfied with this circuit. Different steering arrange-
ments may be used to select independently the guard
times for tone-present (t
This may be necessary to meet system specifications
that place both accept and reject limits on both tone
duration and interdigit pause.
Guard time adjustment also allows the designer to tai-
lor system parameters such as talkoff and noise immu-
nity. Increasing t
since it reduces the probability that tones simulated by
speech will maintain signal condition long enough to be
Pin Functions
* -02 only. Connect to V
REC
Pin
1
2
3
4
5
6
7
8
9
10
11-14 Q1, Q2, Tri-statable data outputs. When enabled by OE, provides the code corresponding to the last valid tone pair
15
16
17
18
of 40 ms would be 300 kΩ. A typical circuit using
Name
Q3, Q4 received (see Tone Decoding table on page 5).
OSC1
OSC2
St/GT
INH*
V
PD*
VSS
StD
IN+
ESt
V
IN-
GS
OE
REF
DD
SS
for -01 version
Non-inverting input
Inverting input
Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail.
Inhibits detection of tones representing keys A, B, C, and D.
Power down. Logic high powers down the device and inhibits the oscillator. Internal pulldown.
Clock input
Clock output
Negative power supply (normally connected to 0 V).
Tri-statable output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is
updated. Returns to logic low when the voltage on St/GT falls below VTSt.
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (signal
condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the
detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT
output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St. (See
Common Crystal Connection on page 5).
Positive power supply. (Normally connected to +5V.)
t
t
REC
GTP
REC
@ 0.67 RC
= t
improves talkoff performance,
DP
GTP
+ t
) and tone-absent (t
GTP
3.579545 MHz crystal connected between these pins completes the internal oscillator.
www.clare.com
GTA
).
Connections to the front-end differential amplifier.
registered. On the other hand, a relatively short t
with a long t
noisy environments where fast acquisition time and
immunity to dropouts would be required. Design infor-
mation for guard time adjustment is shown in the
Guard Time Adjustment below.
Power-down and Inhibit Mode (-02 only)
A logic high applied to pin 6 (PD) will place the device
into standby mode to minimize power consumption. It
Figure 5 Guard Time Adjustment
Description
DO
would be appropriate for extremely
REC
Rev. 3