PEB 2466 H V2.2 Infineon Technologies, PEB 2466 H V2.2 Datasheet

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PEB 2466 H V2.2

Manufacturer Part Number
PEB 2466 H V2.2
Description
IC SICOFI-4 SGL CHIP CMOS MQFP64
Manufacturer
Infineon Technologies
Series
SICOFI®r
Datasheet

Specifications of PEB 2466 H V2.2

Function
CODEC Filter
Interface
PCM, SPI
Number Of Circuits
4
Voltage - Supply
5V
Current - Supply
26mA
Power (watts)
130mW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-QFP
Includes
Advanced On-Chip Functions, Digital Signal Processing (DSP) Technique, Level Metering, Tone Generators
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2466HV2.2XT
PEB2466HV22NP
PEB2466HV22XP
SP000007516
SP000007517
Hard wa r e R e fer enc e Manual , D S 1, F eb. 2001
®
S I C O F I
4 - µ C
F o u r C h a n n e l C o d e c
F i l t e r w i t h P C M a n d
M i c r o c o n t r o l l e r I n t e r f a c e
P E B 2 46 6 V e rs io n 2.2
P E F 2 4 66 V ers io n 2.2
Wired
C om m un ic at io n s
N e v e r
s t o p
t h i n k i n g .

Related parts for PEB 2466 H V2.2

PEB 2466 H V2.2 Summary of contents

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Hard fer enc e Manual , eb. 2001 ® ...

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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...

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Hard Ref er enc e M anual eb. 2001 ® ...

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... PEF 2466 Revision History: Previous Version: Page Subjects (major changes since last revision) For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com ® ® ® ABM ...

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Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 5.1.2 Analog Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 9 Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Figures ® Figure 1 SICOFI 4-µC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of Tables Table 1 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Preface This document provides detailed technical information about the SICOFI intended for anyone considering or using the device for system design or board layout for a broad range of analog telephony applications. All content applies to both the standard PEB ...

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Overview The four-channel codec filter PEB 2466 SICOFI which provides independent filter structures for all channels. Its analog I/O pins are used to connect to external subscriber line interface circuits (SLICs). Their signals are internally routed to the analog-to-digital ...

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Four Channel Codec Filter with PCM and Microcontroller Interface ® SICOFI 4-µC Version 2.2 1.1 Features • Four-channel single chip codec with digital filters • High analog driving capability (300 direct driving of transformers • Digital Signal Processing (DSP) technique ...

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Logic Symbol Channel 1 Channel 2 Analog Interface Channel 3 Channel 4 Channel 1 Signaling Interface Ch. 1&2 Channel 2 ® Figure 2 SICOFI 4-µC Logic Symbol 1.3 Typical Applications Many applications will benefit from the versatility of the ...

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Pin Descriptions 2.1 Pin Diagram (top view IN1 GNDA1 OUT1 V 52 DDA12 V 53 OUT2 GNDA2 54 ...

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Pin Definitions and Functions Table 1 Pin Definitions and Functions Pin Symbol Type Function 1 SI3_1 I Signaling Input, Channel 3 Pin 1 2 SI3_0 I Signaling Input, Channel 3 Pin 0 3 SB3_2 I/O Bi-directional Signaling, Channel 3 ...

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Pin Symbol Type Function Digital Ground 21 GNDD I Ground reference for all digital signals. Internally isolated from GNDA1,2,3,4. Master Clock Input 1536, 2048, 4096 or 8192 kHz must be applied for any 22 MCLK I operation (selected in Register ...

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Pin Symbol Type Function Chopper Clock Output 1 33 CHCLK1 O Provides programmable (2 … 28 ms) output signal (synchronous to MCLK). Interrupt Output, Channels 1 and 2 34 INT12 O Active high. 35 SI1_1 I Signaling Input Channel 1, ...

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Pin Symbol Type Function Analog Ground, Channel 2 54 GNDA2 I Not internally connected to GNDD or GNDA 1,3,4. Analog Voice (Voltage) Input, Channel IN2 Requires a coupling capacitor > the SLIC. Reference Voltage ...

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Functional Description The telephone subscriber loop is a bi-directional two-wire line. The Subscriber Line Interface Circuit (SLIC) on the network side converts the two-wire interface to a four-wire interface with separate receive and transmit signals, which connect to the ...

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PEB 2466, SICOFI4-µC V ADC Hardware IN1 Filters V DAC OUT1 V ADC Hardware IN2 Filters V DAC OUT2 V ADC Hardware IN3 Filters V DAC OUT3 V ADC Hardware IN4 Filters V DAC OUT4 MCLK PLL, CHCLK1 Clocking CHCLK2 ...

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Operational Description Each channel of the SICOFI “Operating”. These states can be switched by programming Bit 0 (PU) in the channel-specific configuration register CR1. “Standby” power-saving state. Keeping all unused channels in this state reduces the overall ...

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Table 2 Register Values and Accessibility Register CR0 ... CR4 XR0 ... XR7 CRAM Table 3 Input and Output Pin Behavior Pin DIN DOUT high impedance DRA, DRB DXA, DXB high impedance TCA#, TCB OUT1 OUT2 high ...

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Table 4 Power Dissipation No. of Channels Operating None 4.2 Transmission Characteristics 4.2.1 Overload Point The overload point of the SICOFI amplitude of a sine wave level of 1.572 Vrms. Higher input signal levels will be ...

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Compressor Gain Relative to Coding Law The µ-Law compressor unit of the SICOFI has to be considered for the total gain calculation. The accumulated gain of all programmable transmit filters (AX1+AX2+FRX) must not exceed the device ...

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Operating Conditions The specifications to which the SICOFI Specification to guardband various SLIC implementations. The guaranteed transmission characteristics of the SICOFI design will meet the ITU-T specification. The figures in this document are based on the subscriber-line board requirements. ...

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Gain Accuracy Table 7 Gain Accuracy Parameter Symbol G Absolute Gain Variation with Temperature Variation with Supply Voltage Variation with Analog Gain 4.2.6 Gain Tracking (Receive and Transmit) The gain deviation for a 1014 Hz sine-wave input signal will ...

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Frequency Response Table 9 Attenuation with Frequency in Transmit and Receive Direction Receive Loss Input Frequency min 100 Hz 0 100 Hz to 200 Hz 0 200 Hz to 300 Hz -0.125 300 Hz to 3.0 ...

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Group Delay Distortion with Frequency The Group Delay Distortion in transmit and receive direction will stay within the limits shown in Table 11. Group Delay Distortion values are referenced to the minimum value of Group Delay (T min). G ...

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Harmonic and Intermodulation Distortion Table 14 Harmonic and Intermodulation Distortion Parameter Symbol Harmonic Distortion order Intermodulation R IMD 2 R IMD 3 4.2.11 Total Distortion Table 15 Signal-to-Total Distortion Ratio Measured with Sine ...

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Table 16 Signal-to-Total Distortion Ratio Measured with Noise Input Level Symbol -55 dB S/D -40 dB S/D -34 dB S/D -27 dB S S/D 40 36.7 dB 34.3 30 29.7 20 14.7 10 ...

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Single Frequency Distortion Test Input Signal Receive Direction Transmit Direction Any resulting signal with a frequency different from the test input signal will stay at least 28 dB below the input signal level. 4.2.13 Overload Compression This is measured ...

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Out-of-Band Discrimination in Transmit Direction With any 0 dBm0 sine-wave signal below 100 Hz and in the range from 3.4 kHz to 100 kHz (out-of-band signal) applied to an analog input (V frequency component at the digital output will ...

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Out-of-Band Discrimination in Receive Direction With any 0 dBm0 sine-wave frequency in the range from 300 Hz to 3.99 kHz applied to the digital input (PCM time slot), the level of any resulting out-of-band signal at the analog output ...

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Out-of-Band Idle Channel Noise at Analog Output With an idle code (any sequence of constant PCM octets) applied to the digital input, the level of any resulting out-of-band power spectral density at the analog output, measured with 3 kHz ...

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Transhybrid Loss The quality of Transhybrid-Balancing is very sensitive to deviations in gain, group delay, and deviations inherent to the A/D- and D/A-converters, as well as to all external components used on a linecard (SLIC, OP’s etc.). Transhybrid loss ...

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Interface Description ® The SICOFI 4-µC provides four interfaces: • Analog Interface, • PCM Interface, • Signaling Interface, and • Serial Microcontroller Interface. A general description of these interface is given in the Product Overview, Chapter 4. Refer to ...

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SLIC 1 > 39nF Load 100nF SLIC 2 100nF > 39nF R Load µ Ext1 ...

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Analog Interface Pins Table 21 Analog Interface Pins Symbol Pin V 49 Analog Input, Channel 1, 2 IN1 Requires a coupling capacitor > the SLIC, see Figure 16 IN2 V 58 Analog Input, Channel 3, ...

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PCM Interface ® The SICOFI 4-µC provides an industry–standard PCM Interface with access to two PCM highways. The PCM Interface has the following features: • Data rate from 128 kbit Mbit/s per highway, • 128 ...

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Table 23 PCM Register Configuration Example Channel CR4 1 0000 0000 2 0000 1111 3 0000 1000 4 0001 1010 all XR6=0000 0000; single clock mode, no PCM offset; PCLK=2048 kHz. FSC PCLK DRA DXA TCA# ...

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FSC Clock 0 PCLK DRA Bit High 'Z' DXA TCA# Figure 18 PCM Interface Example: Detail A The pins DRA/B and DXA/B may be strapped together to form a multiplexed bi-directional PCM port. 5.3 Signaling Interface ® The SICOFI 4-µC ...

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Signaling Interface Pins SLIC Operating Mode Off-Hook Det. Ground Key Det. Ring Relay Status LED SLIC Operating Mode Off-Hook Det. Ground Key Det. Ring Relay Status LED Figure 19 Signaling Example: ...

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Table 24 Signaling Interface: Pins and Functions for SLIC Interfaces Symbol Pin Ch1 Ch2 SIx_0 36 47 SIx_1 35 48 SOx_0 41 42 SOx_1 40 43 SBx_0 39 44 SBx_1 38 45 SBx_2 37 46 INT12 34 INT34 - 5.3.2 ...

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Table 25 Clock Programming CHCLK1 XR4.Field T Output (Pin 33) 0000 High level (+5V) Clock period = T *2ms 0001 to 1110 (min. 2 ms, max. 28 ms) 1111 Low level (0V) 5.4 Serial Microcontroller Interface The Serial Microcontroller Interface ...

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Serial Microcontroller Interface Pins Table 26 Serial Microcontroller Interface: Pins and Functions Symbol Pin Function CS# 17 Chip Select, enable to read or write data, active low. DCLK 18 Data Clock, shifts data from or to device; max. clock ...

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CS# DCLK DIN Read Command High 'Z' DOUT Figure 22 Example for a One-Byte Read Access For byte-by-byte transfer, the high time of DCLK can be prolonged, resulting in a user-defined ...

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Three-Wire Access DIN and DOUT may be strapped together and connected to a single I/O pin of the microcontroller. The interface remains fully functional with only three wire connections. After every command CS# must be set to ’1’. CS# ...

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Programming Overview The transmission characteristics and interfaces of the PEB 2466 can be adapted to various environments. Configuring the functional blocks and programming the digital filter behavior is accomplished by loading values to the Configuration Registers and the Coefficient ...

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Register Maps Table 28 Read Access to Common Configuration Register (XR) Map Bit 7 Bit 6 XR0 SI4_1 SI4_0 XR1 SB4_1 SB4_0 XR2 PSB4_1 PSB4_0 XR3 SB4_2 SB3_2 XR4 Signal Debounce XR5 MCLK-SEL XR6 C-Mode X-S XR7 OF7 OF6 ...

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CRAM Structure Coefficient RAM (CRAM) is used to store the individual coefficients calculated for each channel. The coefficients can be written and read through the Microcontroller Interface. The IM, FRX, FRR, AX, AR, TG1, TG2, and TH coefficients are ...

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Table 32 Coefficient RAM (CRAM) Structure per Set TH Part 1 TH Part 2 TH Part 3 6.2 Types of Commands and Data Bytes Coefficients and register contents are programmed and accessed through command sequences via the Microcontroller Interface. There ...

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Application Hints 7.1 Support Tools 7.1.1 Development Board The Evaluation Package EASY 2466 includes the following hardware: ® • One SICOFI 4-µC Evaluation Board STUT 2466 with connectors for four optional SLIC daughter cards and BNC connectors to a ...

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Guidelines for Board Design 7.2.1 Filter Capacitors • For high frequency noise rejection, use 100 nF SMD ceramic capacitors on pins and DDA12 DDA34 DDREF are recommended. • Use one 100 nF SMD ceramic capacitor ...

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Proposal for SICOFI For a new layout design it is recommended to use a separate ground-layer which gives the possibilty to connect all ground-pins of the SICOFI ohmic together. Furthermore, an optimum board layout should follow these recommendations • ...

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Electrical Characteristics and Timing Diagrams 8.1 Absolute Maximum Ratings Parameter V referred to GNDD DD GNDA to GNDD Analog input and output voltage V Referred Referred to GNDA = 0 V All digital input ...

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Operating Range 5%; GNDD = 0 V; GNDA = °C to +70 °C (PEF 2466: -40 °C to +85 °C) A Parameter V supply current: DD Standby (PEB 2466) ...

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Analog Interface 5%; GNDD = 0 V; GNDA = °C to +70 °C (PEF 2466: -40 °C to +85 °C) A Parameter Input resistance PEF 2466 PEB 2466 Output ...

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PCM-Interface Timing 8.6.1 Single Clocking Mode t PCLK 50% PCLK t t FSC_S FSC t t DR_S DR_H DRA/B DXA/B TCA#/TCB# Figure 29 PCM Interface Timing in Single Clocking Mode Parameter Period of PCLK PCLK high time Period FSC ...

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Double Clocking Mode t PCLK 50% PCLK t t FSC_H FSC_S FSC t t DR_S DRA/B DXA/B TCA#/TCB# Figure 30 PCM Interface Timing in Double Clocking Mode Parameter Period of PCLK PCLK high time Period FSC FSC setup time ...

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Microcontroller Interface Timing t DCLK 50% DCLK t CS_S CS DIN_S DIN_H DIN DOUT Figure 31 Timing of the Microcontroller Interface Parameter Period of DCLK DCLK high time CS# setup time CS# hold time DIN setup time ...

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Signaling Interface Timing 8.8.1 Timing from the DCLK DIN SO/SB Output SB (Output Input) SB (Input Output) Figure 32 Signaling Output Timing (data downstream) Parameter Symbol 1) SO/SB delay time SB to ‘Z’ - time SB to ‘drive’-time 1) ...

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Test Modes ® Each SICOFI 4-µC channel has four test loops that feed the analog input signal back to the analog output (analog test loops), and five test loops that feed the PCM input signal back to the PCM ...

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Digital Loops The digital loops feed signals from the receive path back to the transmit path. There are five digital loops, which are shown in Figure 34. Analog AGX ADC Input IM2 Analog AGR DAC Output Figure 34 Digital ...

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Cut-Off’s The transmit path and the receive path can be cut off at two locations each. Figure 35 shows the locations in the signal paths. Analog AGX ADC Input IM2 COR4M Analog AGR DAC Output Figure 35 Cut-Off’s Table ...

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Package Outlines P-MQFP-64 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Hardware Reference Manual 56 PEB 2466 PEF 2466 Package ...

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Glossary • AC ADC CMOS CO COT CRAM DAC DC DLC DSP DTMF FIR FTTC IIR IOM-2 ITU ITU-T PBX PCM PSTN PTT QSICOS RITL RT SICOFI SLIC t/r Hardware Reference Manual Alternating Current Analog-to-Digital Converter Complementary Metal Oxide ...

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Index Symbols µ-Law . . . . . . . . . . . . . . . 2, 11, 14, 19, 30 µ-Law mode . . . . . . . . . . . . . . . ...

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COP . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 COP command sequences ...

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Functional blocks . . . . . . . . . . . . . . . . . 39 G Gain . . . . . . . . . . . . . . . . . . ...

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O On-/off-hook detection . . . . . . . . . . . . . 10 Operating conditions Operating range . . . . ...

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Registers Reset input pin . . . . . . . . . . . . ...

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Test relays . . . . . . . . . . . . . . . . . . . . . . 10 TG1 and TG2 . . . . . . . . . . . . ...

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