PEB 3081 H V1.4 Infineon Technologies, PEB 3081 H V1.4 Datasheet - Page 118

• Manufacturer Part Number: PEB 3081 H V1.4
• Description: IC S-BUS INTERFACE EXT MQFP44
• Manufacturer: Infineon Technologies

Specifications of PEB 3081 H V1.4

• Function: S / T Bus Interface Transceiver
• Interface: IOM-2, ISDN, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-QFP
• Includes: D-Channel Access Control, Monitor Channel Handler
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3081HV1.4XT; PEB3081HV14XP; SP000007583; SP000007584

Asynchronous Awake (LT-S, NT, Int. NT mode)
The transceiver is in power down mode (deactivated state) and MODE1.CFS=1
(TR_CONF0.LDD is don’t care in this case). Due to any signal on the line the level detect
circuit will asynchronously pull the DU line on IOM-2 to “0” which is deactivated again
after 2 ms if the oscillator is fully operational. If the oscillator is just starting up in
operational mode, the 2 ms duration is extended correspondingly.
3.8
The AUX interface provides various functions, which depend on the operation mode (TE,
LT-T, LT-S, NT or intelligent NT mode) selected by pins MODE0 and MODE1/EAW (see
Table
by the host.
Table 14
Pin
AUX0
AUX1
AUX2
General Purpose I/O AUX0-2 (TE, Int. NT mode)
These pins can be used as programmable I/O lines.
As inputs (AOE.OEx=1) the state at the pin is latched in when the host performes read
operation to register ARX.
As outputs (AOE.OEx=0) the value in register ATX is driven on the pins with a minimum
delay after the write operation to this register is performed. They can be configured as
open drain (ACFG1.ODx=0) or push/pull outputs (ACFG1.ODx=1). The status (’1’ or ’0’)
at output pins can be read back from register ARX, which may be different from the ATX
value, e.g. if another device drives a different level.
Channel Select CH0-2 (LT-T, LT-S, NT mode)
In linecard mode one FSC frame is a multiplex of up to eight IOM-2 channels, each of
them consisting of B1-, B2-, MONITOR-, D- and C/I-channel and MR- and MX-bits.
One of eight channels on the IOM-2 interface is selected by CH0-2. These pins must be
strapped to VDD or VSS according to
Data Sheet
14). After reset the pins are switched as inputs until further configuration is done
Auxiliary Interface
AUX Pin Functions
TE, Int. NT mode
AUX0 (i/o)
AUX1 (i/o)
AUX2 (i/o)
Table
118
15.
Description of Functional Blocks
LT-T, LT-S, NT mode
CH0 (i)
CH1 (i)
CH2 (i)
PEB 3081
2003-02-04
SBCX-X