PEB 3081 H V1.4 Infineon Technologies, PEB 3081 H V1.4 Datasheet - Page 41

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PEB 3081 H V1.4

Manufacturer Part Number
PEB 3081 H V1.4
Description
IC S-BUS INTERFACE EXT MQFP44
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB 3081 H V1.4

Function
S / T Bus Interface Transceiver
Interface
IOM-2, ISDN, SCI
Number Of Circuits
1
Voltage - Supply
3.3V
Current - Supply
30mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-QFP
Includes
D-Channel Access Control, Monitor Channel Handler
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Other names
PEB3081HV1.4XT
PEB3081HV14XP
SP000007583
SP000007584
SBCX-X
PEB 3081
Description of Functional Blocks
TE Mode
After multiframe synchronization has been established, the Q data will be inserted at the
upstream (TE ® NT) F
bit position in each 5th S/T frame (see
Table
7).
A
When synchronization is not achieved or lost, each received F
bit is mirrored to the next
A
transmitted F
bit.
A
Multiframe synchronization is achieved after two complete multiframes have been
detected with reference to F
/N bit and M bit positions. Multiframe synchronization is lost
A
if bit errors in F
/N bit or M bit positions have been detected in two consecutive
A
multiframes. The synchronization state is indicated by the MSYN bit in the S/Q-channel
receive register (SQRR1).
The multiframe synchronization can be enabled or disabled by programming the MFEN
bit in the S/Q-channel transmit register (SQXR1).
NT Mode
The transceiver in NT mode starts multiframing if SQXR1.MFEN is set.
After multiframe synchronization has been established in the TE, the Q data will be
inserted at the upstream (TE ® NT) F
bit position by the TE in each 5th S/T frame, the
A
S data will be inserted at the downstream (NT ® TE) S bit position in each S/T frame
(see
Table
7).
Interrupt Handling for Multiframing
To trigger the microcontroller for a multiframe access an interrupt can be generated once
per multiframe (SQW) or if the received S-channels (TE) or Q-channel (NT) have
changed (SQC).
In both cases the microcontroller has access to the multiframe within the duration of one
multiframe (5 ms).
Data Sheet
41
2003-02-04

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