PEB 3081 H V1.4 Infineon Technologies, PEB 3081 H V1.4 Datasheet - Page 50

• Manufacturer Part Number: PEB 3081 H V1.4
• Description: IC S-BUS INTERFACE EXT MQFP44
• Manufacturer: Infineon Technologies

Specifications of PEB 3081 H V1.4

• Function: S / T Bus Interface Transceiver
• Interface: IOM-2, ISDN, SCI
• Number Of Circuits: 1
• Voltage - Supply: 3.3V
• Current - Supply: 30mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-QFP
• Includes: D-Channel Access Control, Monitor Channel Handler
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEB3081HV1.4XT; PEB3081HV14XP; SP000007583; SP000007584

3.3.7
The S/T transmitter is shifted by two S/T bits minus 7 oscillator periods (plus analog
delay plus delay of the external circuitry) with respect to the received frame. To
compensate additional delay introduced into the receive and transmit path by the
external circuit the delay of the transmit data can be reduced by another two oscillator
periods (2 x 130 ns). Therefore PDS of the TR_CONF2 register must be programmed to
’1’. This delay compensation might be necessary in order to comply with the "total phase
deviation input to output" requirement of ITU-T recommendation I.430 which specifies a
phase deviation in the range of – 7% to + 15% of a bit period.
3.3.8
If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas
if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks,
including the IOM-2 interface, are stopped (DD, DU are ’high’, DCL and BCL are ’low’).
An activation initiated from the exchange side will have the consequence that a clock
signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set
to ’1’ the microcontroller has to take care of an interrupt caused by the level detect circuit
(ISTATR.LD)
From the terminal side an activation must be started by setting and resetting the SPU-bit
in the IOM_CR register and writing TIM to the CIX0 register or by resetting
MODE1.CFS=0.
3.3.9
The layer-1 part of the SBCX-X can be enabled/disabled by configuration (see
Figure
By default all layer-1 functions with the exception of the transmitter buffer is enabled
(DIS_TR = ’0’, DIS_TX = ’1’). With several terminals connected to the S/T interface,
another terminal may keep the interface activated although the SBCX-X does not
establish a connection. The receiver will monitor for incoming calls in this configuration.
If the transceiver is disabled (DIS_TR = ’1’) all layer-1 functions are disabled including
the level detection circuit of the receiver. In this case the power consumption of the
Layer-1 is reduced to a minimum. The DCL and FSC pins become input.
Data Sheet
27) with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX .
S/T Interface Delay Compensation (TE/LT-T Mode)
Level Detection Power Down
Transceiver Enable/Disable
50
Description of Functional Blocks
PEB 3081
2003-02-04
SBCX-X